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For multi-channel high-speed image data of certain space remote sensing camera, this paper proposed a new image data acquisition and storage system. First of all, the system uses Field-Programmable Gate Array(FPGA) controlling synchronous dynamic random access memory(SDRAM) array to realize the cache of image data, then according to the received commands, sends certain channel's image data to the...
This paper is concerned with the guaranteed cost fault tolerant control of networked control systems with both time-varying network-induces delay and data dropout. Using LMI approach, new criteria are proposed for the networked guaranteed cost controller design. The new criteria are irrelevant to the bound of the derivative of the delay, no constrain is imposed to the matrix structure. A numerical...
This paper considered the non-fragile guaranteed cost fault tolerant control problem of networked control systems with both fast-varying network-induces delay and data dropout. Using Lyapunov stability theory and the linear matrix inequality (LMI) approach, new criteria are proposed for the non-fragile controller design. A simulation example is given to verify the validity of the proposed method.
This paper presents a new at-speed logic built-in self-test (BIST) architecture supporting two launch-on-capture schemes, namely aligned double-capture and staggered double-capture, for testing multi-frequency synchronous and asynchronous clock domains in a scan-based BIST design. The proposed architecture also includes BIST debug and diagnosis circuitry to help locate BIST failures. The aligned scheme...
This paper proposes a full custom design of a 9-write and 17-read multi-port register file. The proposed register file can fulfill one read-after-write access in one system cycle with a synchronous read and an asynchronous write. The design employs a single-ended sense amplifier and a high-speed SCL address-decoder as write decoder controlled by VCLK, which is generated through a novel positive edge...
We present a capacitance deviation-to-digital converter (CDC) for the thin membrane transducers (TMT) used for bio-molecular detection. Our CDC consists of a capacitance deviation-to-time converter (CTC), time-stretchers, and a time-to-digital converter (TDC). The time-stretchers are innovatively adopted to achieve higher resolution of the CDC with expanse of moderate power consumption. Designed and...
Time Petri net and timed Petri net, in which transactions are constrained with time info, are widely used in task scheduling and performance analysis, whereas they are not effective enough for project performance analysis. Timing constraint Petri net (TcPN for short) is proposed in which places are endued with time delaying domain and time persisting domain simultaneously. Furthermore, all time constraints...
Five different designs for a hypothetical five-inch wafer with an array of 8*8 cells are presented. The networks are simulated using HSPICE for comparison of power dissipation, delay, and skew. It is found that the large physical dimensions of a wafer scale system require that the signal interconnections be treated as transmission lines with finite delays in order to provide an accurate simulation...
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