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This paper compares readout powers and operating frequencies among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM. The conventional 8T SRAM has the least transistor count, and is the most area efficient. However, the readout power becomes large and the cycle time increases due to peripheral circuits. The 10T single-end SRAM is our proposed SRAM, in which a dedicated inverter...
Since the very beginning of the flash memory era, the market has been dominated by the floating gate technology. However, as floating gate flash continues along a very steep scaling path, more and more barriers start to appear, limiting further scaling possibilities of the technology. At the same time, other concepts are preparing to take over. This paper concentrates on the prospect of high-k materials...
A slew rate controlled output driver adopting delay compensation method is implemented using 0.18 µm CMOS process for storage device interface. Phase-Locked Loop is used to generate compensation current and constant delay time. Compensation current reduces the slew rate variation over process, voltage and temperature variation in output driver. To generate constant delay time, the replica of VCO in...
A new self calibrating and adjustable CMOS pad driver for improved electromagnetic compatibility is presented. A variable, user defined output slew rate is achieved, independent of process, supply voltage, temperature and load variations. Measurements on a test chip proved the functionality and the improvements of the driver. For example, the deviation of a slope time from the nominal value by varying...
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