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A SiC BJT model including quasi-saturation effects is proposed in this paper. The model limits the number of parameters required for the Gummel-Poon model and the model parameters have been extracted from experimental plots. The modeling results are then implemented in a circuit simulator such as Saber to build a SiC BJT model. Validity of the model is confirmed by comparing the model with experimental...
Spacecrafts in geostationary Earth orbit and low Earth polar orbit experience temperatures in the range of 180°C to 80°C [1, 2] depending on the orbit. Solar cells are mounted on light weight aluminum honeycomb panels which are deployed and Sun pointed in on-orbit operation. Solar panels charge batteries and supply power to the satellite during sunlit period and batteries supply power during eclipse...
This work reports on the characterization of the Multi-Pixel Photon Counter (MPPC) detectors as a function of the temperature and bias voltage. Devices of 1×1 mm2 and 3×3 mm2 total area and 50×50 μm2 μcell size produced by Hamamatsu Photonics have been studied. The temperature has been varied from -110°C to -50°C using a cryostat cooled by liquid nitrogen and from 0 to 38°C using a climatic chamber...
We report on the progress in the Electron-Counting-Capacitance-Standard (ECCS) experiment. In particular, we address electrostatic breakdown in metallic single-electron tunneling (SET) structures fabricated on high-quality insulating substrates, An approach was developed via on-chip silicon shunts protecting the high-ohmic nanoscale tunnel junctions against damage.
This paper proposes novel multiple-valued (MV) logic gates by using asymmetric single-electron transistors (SETs). Asymmetric single-electron transistors have two tunneling junctions with largely different resistances and capacitances. We fully exploited the unique Coulomb staircase characteristic of asymmetric SETs to compactly finish logic operations. We build MV literal gates with wide range of...
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
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