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Cryptographic hash functions have many security based applications, particularly in message authentication codes (MACs), digital signatures and data integrity. Secure Hash Algorithm-3 (SHA-3) is a new cryptographic hash algorithm that was selected on 2nd Oct '12 after a five year public contest organized by the National Institute of Standards and Technology (NIST), USA. This paper provides a unique...
Modern cloud storage requires a high throughput and low latency data protection system, which is usually implemented with an Advanced Encryption Standard (AES) hardware accelerator connected with CPU through PCI Express (PCIe). However, most existing systems cannot simultaneously achieve high throughput and low latency, as they impose conflicting requirements to the block size of packets used in PCIe...
In this paper, a throughput enhanced version of a new True Random Bit Generator (TRBG) based on a time-delay sampled-data system is proposed. This new TRBG has both analog and digital parts, which provides the dynamic behavior and the sample and delay process, respectively. The simple system equations and the ease of implementation make this new TRBG very practical. The only required components for...
This letter presents a new efficient architecture for high-speed advanced encryption standard (AES) encryptor. This technique is implemented using composite field arithmetic byte substitution, where higher efficiency is achieved by merging and location rearrangement of different operations required in the steps of encryption. The proposed architecture is presented with multistage subpipelined architecture...
Compact and high-speed hardware architectures for the 192-bit hash function Tiger are proposed and their gate counts and throughputs are evaluated using a 90-nm CMOS standard cell library. The implementations achieve practical performances of 22.5 K with 2.2 Gbps and 46.4 Kgates with 6.95 Gbps. These throughputs are 1.5-2 times higher than those of the SHA hash family SHA-256/-512, but the hardware...
The nanoscale technology makes the design concept of the sea of processors possible in the coming billion transistor era for high performance implementations. In order to solve the scalability, complexity and timing problem of the communication between these processors in a large scale SoC (System on a Chip) implementation, the NoC (Network on a Chip) or OCN (On-Chip Network) paradigm, a replacement...
The security hash algorithm 512 (SHA-512), which is used to verify the integrity of a message, involves computation iterations on data. The huge computation delay generated in that iteration limits the entire throughput of the system, and makes it difficult to pipeline the computation. To shorten the computation time in an iteration of the main loop, we used the data forwarding method. Here we introduce...
Multi-cipher and multi-mode reconfigurable cryptosystems are widely used for hardware acceleration in modern security protocols, such as SSL and IPsec, but there has been hardly any work which can process multiple cipher algorithms with varied block lengths, key lengths and operation modes at a session of communication owing to the lack of suitable scheduling algorithms for the crypto-coprocessors...
We present an AES cipher implementation that is based on the BlockRAM and DSP units embedded within Xilinx's Virtex-5 FPGAs. An iterative "basic" module outputs a 32 bit column of an AES round each clock cycle, with a throughput of 1.76 Gbit/s when processing two 128 bit inputs. This construct is replicated four times for a 128 bit datapath for a full AES round with 6.21 Gbit/s throughput...
This paper describes VLSI architectures for multiplication modulo p, where p is a Fermat prime. With increasing p, ROM based methods become unattractive for integration due to excessive memory requirements. Two new methods are discussed and compared to ROM implementations with regard to their speed/complexity behaviour. The first method is based on a (n + 1) x (n + 1) bit array multiplier, the second...
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