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Modern vehicles are equipped with several interconnected sensors on board for monitoring and diagnosis purposes; their availability is a main driver for the development of novel applications in the smart vehicle domain. In this paper, we propose a Docker container-based platform as solution for implementing customized smart car applications. Through a proof-of-concept prototype—developed on a Raspberry...
The use of hardware accelerators to increase the performance of parallel applications is very common nowadays. For a number of reasons, however, the access to local accelerators is not always feasible (e.g., lack of space or cost). It would also be the case that some applications benefit from having access to more accelerators than the physically possible. To address all these concerns, middleware...
As the users on the cloud network increase, the consumption of the Compute, Network and Storage resources also increases. This leads to increase in the cost of deployment, configuration and maintenance. Hence, the Capital Expenditure (CAPEX) and Operational Expenditure (OPEX) of the organization providing the cloud network increases. Network Function Virtualization (NFV) is a technology which virtualizes...
Post-silicon validation is one of the most important parts of the microprocessor prototype chip lifecycle. It is the last chance for debug engineers to detect defects and bugs that escaped pre-silicon verification, before the chip is released to the market. Effective solutions are required to harness the peak performance of the hardware prototype and evaluate whether the microprocessor chip is fully...
This paper describes a novel scheme which enables scaling of cellular node applications without disrupting session continuity. With this scheme, states of node applications, including User Equipment (UE) states and transport protocol states, are maintained during scaling operations that are possible in a virtualized environment. A prototype of Mobility Management Entity (MME) of Evolved Packet Core...
Large applications executing on Grid or cluster architectures consisting of hundreds or thousands of computational Nodes create problems with respect to reliability. The ATM Machine is one of such Application. There is an increasing need for fault tolerance capabilities in logic devices brought about by the scaling of transistors to ever smaller geometrics. This paper presents a secure hypervisor...
There is an increasing need for fault tolerance capabilities in logic devices brought about by the scaling of transistors to ever smaller geometries. This paper presents a hypervisor-based replication approach that can be applied to commodity hardware to allow for virtually lockstepped execution. It offers many of the benefits of hardware-based lockstep while being cheaper and easier to implement...
Improved resource utilization and fault tolerance of large-scale HPC systems can be achieved through fine-grained, intelligent, and dynamic resource (re)allocation. We explore components and enabling technologies applicable to creating a system to provide this capability: specifically 1) Scalable fine-grained monitoring and analysis to inform resource allocation decisions, 2) Virtualization to enable...
A new single system image (SSI) system is implemented in order to simplify the complexity of management and programming of clusters. Resource in clusters is integrated by the combination of virtualization and distributed shared memory (DSM), and a single physical machine abstract is achieved for the guest operating system as a result of single system image. The prototype system proves the feasibility...
With the development of computer application technology, devices interfaces are diversified and it makes application development, update and maintenance more difficult. In this paper, we present a virtual device system architecture hierarchical model that is used to make virtual conversion between different physical interfaces. First we introduced the model in details and a user study with network...
This paper presents a novel stateless, virtualized communication engine for sub-microsecond latency. Using a field-programmable-gate-array (FPGA) based prototype we show a latency of 970 ns between two machines with our virtualized engine for low overhead (VELO). The FPGA device is directly connected to the CPUs by a hypertransport link. The described hardware architecture is optimized for small messages...
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