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Optical flow is one of the tools for video content analysis (VCA). The optical flow involves a gradient coprocessor as preprocessing to estimate partial derivative. The gradient processor consists of kernels (masks) to convolute each pixel of image sequences. In hardware implementation of the gradient into FPGA, a multiply accumulate (MAC) is an important technique that is useful for reducing the...
Control the data flow between device interfaces, processing blocks and memories in a vision system is complex in hardware implementation. In the research, high-level synthesis tool is used to design, implement and test the vision system within the context of required control, synchronization, and parameterization on a processor based platform. In addition, both HLS tools and HDL were used for the...
This paper presents the use of local oriented energy features for real-time object tracking on embedded vision systems. Local oriented energy features are extracted using complex Gabor filters. Filtering is carried out across multiple channels with different frequencies and orientations. The effectiveness of the chosen feature set is tested using a mean-shift tracker. Our experiments show that adding...
The purpose of this paper is the design of target recognition system based on machine vision. Through the needs analysis of the system, hardware platform and software platform is built on machine vision. The scheme of machine vision based on PXI bus is put forwarded. The VISION module which is the machine vision of Lab VIEW software is introduced. The target (star) of the image acquisition and target...
The background identification methods are used in many fields like video surveillance and traffic monitoring. In this paper we propose a hardware implementation of the Gaussian Mixture Model algorithm able to perform background identification on HD images. The proposed circuit is based on the OpenCV implementation, particularly suited to improve the initial background learning phase. Bit-width has...
This paper presents a novel binary fully adaptable window for incorporating in a stereo matching System-on-Chip (SoC) architecture. This architecture is fully scalable and parameterizable to allow for custom SoC implementations, as well as rapid prototyping on FPGAs. For each window a binary mask window is generated which selects the supporting pixels in the cost aggregation phase of the SAD algorithm...
This paper presents the implementation and evaluation of a computer vision task on a Field Programmable Gate Array (FPGA). As an experimental approach for an application-specific image-processing problem, it provides results about gained performance and precision compared with similar solutions on General Purpose Processor (GPP) architectures. The problem of detecting Binary Large OBjects (BLOBs)...
Address-event representation (AER) is an emergent hardware technology which shows a high potential for providing in the near future a solid technological substrate for emulating brain-like processing structures. When used for vision, AER sensors and processors are not restricted to capturing and processing still image frames, as in commercial frame-based video technology, but sense and process visual...
This paper presents an event-driven vision system, including a dual-line dynamic vision sensor and a general purpose address-event processor tailored for real-time and highspeed applications. The asynchronous and self-spiking pixels of the dynamic vision sensor are times tamped with high-precision and routed to the processor for flexible and data rate-dependent information processing. The general-purpose...
The integral image is an intermediate image representation that allows rapid calculation of rectangular features at constant speed, irrespective of filter size, and is particularly useful for multi-scale computer vision algorithms like speeded-up robust features (SURF). Although calculation of the integral image involves simple addition operations, the total number of operations is significant due...
We propose a novel framework in which simple and suitable hardware design accompanied with effective software algorithm to boost the performance of an 8-bit MCU-based embedded vision system to the level of a PC-based one. Our goal is to build a small and low cost 8-bit MCU-based embedded vision system in the form of an intelligent sensor to track multiple YUV 24-bit color objects in real time. Our...
Balancing small objects such as a normal pencil on its tip requires rapid feedback control with latencies on the order of milliseconds. Here we describe how a pair of spike-based silicon retina dynamic vision sensors (DVS) is used to provide fast visual feedback for controlling an actuated table to balance an ordinary pencil on its tip. Two DVSs view the pencil from right angles. Movements of the...
Automatic understanding of events happening at a site is the ultimate goal for many visual surveillance systems. Understanding of events requires that certain lower level computer vision tasks be performed. These include foreground detection, labeling foreground parts, and tracking targets. To achieve these tasks, it is necessary to build background subtraction and foreground tracking in the scene...
In this paper, we present a parallel connected component labeling method and its VLSI architecture design. The proposed method can assign labels to three pixels simultaneously for the raster scan input and then generate three label equivalences rapidly. We also present 3 arrays to process all label mergence. Based on the proposed method, we develop the hardware design for realtime application. The...
Balancing a normal pencil on its tip requires rapid feedback control with latencies on the order of milliseconds. This demonstration shows how a pair of spike-based silicon retina dynamic vision sensors (DVS) is used to provide fast visual feedback for controlling an actuated table to balance an ordinary pencil. Two DVSs view the pencil from right angles. Movements of the pencil cause spike address-events...
Zernike moments are trascendental digital image descriptors used in many application areas like biomedical image processing and computer vision due to their good properties of orthogonality and rotation invariance. However, their computation is too expensive and limits its application in practice, overall when real-time constraints are imposed. This work introduces a novel approach to the high-performance...
Template matching is a classical problem in computer vision. It consists in detecting the presence of a given template in a digital image. This task becomes considerably more complex with the invariance to rotation, scale, translation, brightness and contrast (RSTBC). A novel RSTBC-invariant robust template matching algorithm named Ciratefi was recently proposed. However, its execution in a conventional...
A hardware flatform detecting and sorting the faults of cigarette package is designed by using the technology of machine vision. Algorithm and systemic software are also designed according to its characteristics. With stability and accuracy it is of some guiding value to the high speed on-line package detection.
Hardwired acceleration units capable of exploiting the parallelism of images rely on highly customized memory organizations. In this paper we analyze a widely used depth-discontinuity-algorithm applied in stereo vision systems. The main processing kernels are decomposed, and a hardwired acceleration unit is proposed for speeding up the computation. The hardware accelerator includes multiple arithmetic...
Many fatal accidents have happened due to drivers failing to stop at stop signs. A stop sign recognition system could be used to reduce the risk of accidents by warning the driver when a vehicle approaches a stop sign at an unexpected speed. In this paper, we describe the implementation of a real-time vision-based stop sign recognition system on a Xilinx Virtex-4 Field Programmable Gate Array (FPGA)...
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