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The usage of Cellular Automata (CA) for image processing tasks in self-organizing systems is a well known method, but it is a challenge to process such CAs in an embedded hardware efficiently. CAs present a helpful base for the design of both robust and fast solutions for embedded image processing hardware. Therefore, we have developed a system on a chip called ParCA which is a programmable architecture...
Control the data flow between device interfaces, processing blocks and memories in a vision system is complex in hardware implementation. In the research, high-level synthesis tool is used to design, implement and test the vision system within the context of required control, synchronization, and parameterization on a processor based platform. In addition, both HLS tools and HDL were used for the...
In this paper, we propose a Mixed Signal Parallel Multi 1Dimensional Block Matching Algorithm (MSPM-1D-BMA) based motion estimation (ME) processor. In contrast to the typical 2Dimensional full search block matching algorithm (2DFSBMA), the MSPM-1D-BMA based ME processor will greatly reduce the number of data movements in between memories. We employ a voting algorithm in the proposed ME processor to...
This paper presents a new algorithm for nighttime contrast enhancement. The proposed algorithm modifies the traditional histogram equalization algorithm to maintain the color information of the original nighttime images. The algorithm has a low computational cost that makes it suitable for real-time hardware implementation. In addition, its efficient hardware implementation is detailed on a Xilinx...
Based on the group of SONY Company ICX229AK PAL image sensor chipset, PAL integrative camera with VGA interface is designed in this paper. Using the DSP + FPGA + ASIC architecture, it completes the acquisition of the video signal and display, and achieves key technologies of auto-focusing and auto iris in the FPGA. Some new type practical functions such as four images storage, mouse driver, real-time...
In order to increase coding efficiency, a perception-aware H.264/AVC encoder is proposed in this paper. With a different perception models for intra-frames and inter-frames, the initial quantization parameter (QP) is perceptually adjusted to remove perceptual redundancy. Moreover, the associated hardware architectures of the whole encoder and the perception analysis engine are also proposed with hardware...
The computational-intensive demands of H.264 video encoder normally imply to the use of high performance hardware solutions like dedicated multimedia DSP or programmable logic devices. These demands can be even more critical when it is necessary to implement a H.264/SVC (Scalable Video Coding) solution, an emergent encoder standard that provides the generation of flexible and adaptive multi-layer...
Xilinx and Mathworks jointly proposed System Generator (SysGen) and Simulink to accelerate development of DSP (digital signal processing) style applications on Field Programmable Gate Array (FPGA) chips. However, most of developments with Simulink and SysGen end at simulation stage without complete stand-alone implementation on FPGA since these tools do not come up with sufficient IO system libraries...
In this paper, we present a fast implementation of the vector directional distance filter (VDDF) for noise suppression and fine-details preservation in color image, based on FPGA hardware/software (HW/SW) environment. For the ease of implementation, we have proposed some approximations. An efficient hardware implementation is developed to acquire best execution time. After validation, using NiosII...
A novel approach for counting people passing through a region where is surveilled by a parallel-fixed binocular camera is proposed in this paper. Firstly, two virtual counting lines are set to obtain four line space-time gray images. Then an integrated algorithm based on binocular stereovision and regional gray projection is proposed to extract and split overlapped moving objects in complex counting...
Address-event representation (AER) is an emergent hardware technology which shows a high potential for providing in the near future a solid technological substrate for emulating brain-like processing structures. When used for vision, AER sensors and processors are not restricted to capturing and processing still image frames, as in commercial frame-based video technology, but sense and process visual...
In this paper, a novel approach for defects detection in web inspection based on TMS320DM642 DSP development board is proposed. The whole commercial web inspection system can be divided into three major function units: image capture, real-time processing of line-scanned images and the networking transmission. An innovative line-analysis based threshold detection algorithm is presented. The experimental...
Embedded video surveillance has become a large market as the number of installed cameras around us can show. At the same time, video compression technique has been rapidly developed in recent years. As a new generation of video coding compression standard, extensive attention has been given to H.264/AVC. On the other hand, because of good cost-effective and low-power consumption, DSP is widely used...
The increasing amount of data produced in satellites poses a downlink communication problem due to the limited data rate of the downlink. This bottleneck is solved by introducing more and more processing power on-board to compress data to a satisfiable rate. This paper introduces an algorithm which has been developed to compress hyperspectral images at low complexity and describes its mapping to a...
Zernike moments are trascendental digital image descriptors used in many application areas like biomedical image processing and computer vision due to their good properties of orthogonality and rotation invariance. However, their computation is too expensive and limits its application in practice, overall when real-time constraints are imposed. This work introduces a novel approach to the high-performance...
To reduce the bandwidth requirement and the size of frame memory for video decoding, embedding a compressor/decompressor on the chip is a well-known solution. Video compression has been developed for a long time and numbers of algorithm have been proposed. Those algorithms show us that enhancing the complexity can reach better performance. However, algorithm with higher complexity is more difficult...
In this work, the influence of the content of algorithms for primary processing of visual data on methods of their hardware and software implementation is studied. A formal method for construction of architectures of vision systems for solution of different scene recognition problems which are cost-optimal for given performance is presented. Digital signal processors (DSPs) and field programmable...
This paper describes the idea of the multi-core programmable cores architecture for real-time image processing in embedded applications. The authors propose the architecture of a simple 8-bit processor core dedicated to low and intermediate level image operations. Several cores are connected to a common, 128-bit wide data bus by multiplexes and their operation is synchronized. The image data on the...
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