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The usage of Cellular Automata (CA) for image processing tasks in self-organizing systems is a well known method, but it is a challenge to process such CAs in an embedded hardware efficiently. CAs present a helpful base for the design of both robust and fast solutions for embedded image processing hardware. Therefore, we have developed a system on a chip called ParCA which is a programmable architecture...
In view of the complexity and high cost of image processing system, the real-time image processing system based on SOPC (System-on-a-Programmable-Chip) is proposed in this paper. The embedded Nios II soft-core processor is used to collect and process the image and the algorithm which has the features of simplicity and great data quantity and parallelism is implemented by the hardware in FPGA. By this...
This paper presents a novel binary fully adaptable window for incorporating in a stereo matching System-on-Chip (SoC) architecture. This architecture is fully scalable and parameterizable to allow for custom SoC implementations, as well as rapid prototyping on FPGAs. For each window a binary mask window is generated which selects the supporting pixels in the cost aggregation phase of the SAD algorithm...
In this paper motion compensation IP core design based on SOPC technology is researched, which achieves the software hardware co-design method in video decoding to overcome the drawbacks of the software decoding and hardware decoding. The design of hardware modularization which is based on the motion compensation algorithm in MPEG-4 video decoding standard is completed by using verilog HDL language...
In this paper, we propose a real-time platform for the H.264 CODEC with a memory management method, in which we use a preloading mechanism in order to reduce access to external memory. The platform uses an external DDR2 memory (to record the sequence images) and an intelligent memory controller to read the external memory periodically to load another local memory by the macroblocks (of different sizes)...
This work presents the design of a complex image processing IP developed completely in C. We present the latest advanced in ESL-synthesis and demonstrate its main advantages over conventional RT-level flows. In particular we focus on the ability of behavioral synthesis to shorten the design cycle, perform functional verification and explore quickly the design space obtaining multiple dominating implementations...
As the rapid development of computer science and pattern recognition, visual technology is widely applied in industry and daily life. This paper provides a face-recognition hardware implementation based on SOPC, in which custom peripherals, manufacture-provided IP and NiosII processor are connected by Avalon Memory-Mapped Interface. Real time data is transported through Avalon Streaming Interface...
Fractal Image Compression (FIC) is a lossy technique whose features are promising for computer systems with few resources, however, it has been ignored due to the large amount of operations needed to complete the codification. On the other hand, the development of VLSI technology allows for the creation of programmable devices with greater facilities, which not only offer a large gate density to program...
Automatic understanding of events happening at a site is the ultimate goal for many visual surveillance systems. Understanding of events requires that certain lower level computer vision tasks be performed. These include foreground detection, labeling foreground parts, and tracking targets. To achieve these tasks, it is necessary to build background subtraction and foreground tracking in the scene...
This paper presents an 8.69 Mvertices/s, 278 Mpixels/s, 15.7 mm2 tiled-based 3D graphics SoC HW/SW supporting OpenGL ES 1.0 running at 139 MHz. The SoC also includes embedded circuitry to monitor run time characteristics, detect bus protocol error/inefficiency, and capture bus traces at various abstraction levels with compression ratio up to 98%.
In this paper, we propose a novel architecture of photo core transform (PCT) which is used as transformation of image data into frequency domain in HD Photo, an emerging image coding system developed by Microsoft. In order to support various memory bus bandwidths used in system-on-a-chip (SoC) design, an implementation for each bandwidth can be derived based on our architecture. In addition, in order...
The OSSS methodology defines a seamless design flow for embedded HW/SW systems. It enables the effective use of high-level SystemCTM and C++ features like classes (object-oriented design paradigm), templates and method based communication for the description of SW and HW. Furthermore, it supports the OSCI SystemC Synthesis Subset for low-level HW description and HW IP integration. With Fossy we provide...
Bandwidth is always one of the bottlenecks in system-on-a-chip (SoC) systems. In this paper, we propose an efficient architectural design in analyzing the bandwidth of each component in an H.264 design. We decompose the entire H.264 system bandwidths into several modules with predictable coefficients. The derived equations may help designers understand the real cost of each hardware component, thus...
On board image data compression is an important feature of satellite remote sensing payloads. Reconfigurable intellectual property (IP) cores can enable change of functionality or modifications. A new and efficient lossless image compression scheme for space applications is proposed. In this paper, we present a lossless image compression IP core designed using AccelDSP, which gives users high level...
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