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The H.264/AVC intra-frame codec is widely used to compress image/video data for applications like Digital Still Camera (DSC), Digital Video Camera (DVC), Television Studio Broadcast, and Surveillance video. Intra-prediction is one of the top 3 compute-intensive processing functions in the H.264/AVC baseline decoder and, therefore, consumes significant number of compute cycles a processor. In this...
This paper presents a hardware design for the H.264/AVC Eighth-Pixel Chrominance Interpolation Unit that is a part of the Motion Compensation Unit. The architecture was optimized to reach a high throughput through a balanced pipeline and internal parallelism exploration. The design was described in VHDL and synthesized to a Xilinx Virtex2p FPGA. The best performance results achieve an operation frequency...
Median filter is a non-linear filter used in image processing for impulse noise removal during morphological operations, image enhancement and other image processing operations. It finds its typical application in the situations where edges are to be preserved for higher level operations like segmentation, object recognition etc. Real-time applications, such as video and high speed acquisition cameras...
This paper introduces the composition and operating principle of the image test signal generator about HDTV based on CPLD, it explains the logic function design in CPLD and the hardware configuration of this system in detail. The signals produced by this generator accord with the parameter standard of video signal interface about our national High Definition Television. Furthermore, programming with...
Median filter has good capabilities for reducing a variety kind of random noise, and causes less ambiguity than linear smoothing filters under same processing size. In order to suppress the impulse noise of digital video signal and meet the system's needs of real-time, it is of great significance to do fast filtering of image based on hardware. By analyzing the common 3×3 filtering window's mathematical...
Motion Estimation (ME) is the most computationally intensive part in the whole video compression process. The ME algorithms can be divided into full search ME (FS) and fast ME (FME). The FS is not suitable for high definition (HD) frame size videos because its relevant high computation load and hard to deal with complex motions in limited search range. A lot of FME algorithms have been proposed which...
In this work the image is segmented effectively based on texture feature by reducing the noise. For effective image segmentation Expectation-Maximization (EM) algorithm based on Gabor filter is used. The EM algorithm is applied on 2D Ultrasonic image of uterus and tested. The Gabor function has been recognized by its multiresolution properties and the precision of locating the texture features in...
Since Frame Rate Up-Conversion (FRC) is started to be used in recent consumer electronics products like High Definition TV, real-time and low cost implementation of FRC algorithms has become very important. Therefore, in this paper, we propose a low cost hardware architecture for realtime implementation of frame interpolation algorithms. The proposed hardware architecture is reconfigurable and it...
In this paper, we present an efficient H.264 / AVC Intra 16times16 Frame Coder System. The System achieves realtime performance for video conference applications. The INTRA 16times16 is composed by intra 16times16 prediction, integer transform, quantization AC, inverse integer transform, inverse quantization AC, quantization DC, hadamard, inverse quantization DC, and inverse integer transform. The...
In this paper, we present an efficient H.264 / AVC intra 16times16 frame coder system. The system achieves real-time performance for video conference applications. The INTRA 16times16 is composed by intra 16times16 prediction, integer transform, quantization AC, inverse quantization AC, quantization DC, hadamard, inverse quantization DC, and inverse integer transform. The proposed hardware is implemented...
This paper presents novel hardware architecture for real-time implementation of adaptive deblocking filter algorithm used in H.264/AVC baseline profile video coding standard. This hardware is designed to be used as part of a complete H.264 video coding system for video conference applications. We use a novel edge filter ordering in a Macroblock to prevent the deblocking filter hardware from unnecessarily...
Motion estimation (ME) is one of the most time-consuming parts in video encoding system, and significantly affects the output quality of an encoded sequence. In this paper, we present hardware implementation of the Large Diamond Parallel search algorithm. This hardware is designed to be used as part of a complete H.264 video coding system. This architecture is simulated and tested using VHDL and synthesized...
In this paper, we propose a simple binary shape matching algorithm and its hardware implementation. A shape matching algorithm is a method to measure the similarity of objects in an image. This technology is generally used in image retrieval, inspection, and object detection. The proposed method uses a transformation matrix that handles translation, rotation, and scaling. With a combined transformation...
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. For the recently available high definition frame sizes and high frame rates, the computational complexity of full search (FS) ME algorithm is prohibitively high, while the PSNR obtained by fast search ME algorithms is low. Therefore, in this paper, we propose a new ME algorithm and...
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. For the recently available high definition (HD) video formats, the computational complexity of full search (FS) ME algorithm is prohibitively high, whereas the PSNR obtained by fast search ME algorithms is low. Therefore, in this paper, we present dynamically variable step search (DVSS)...
This paper presents a face detection hardware architecture which is based on a newly proposed algorithm using cascaded classifiers with vector angle similarity measurement between the investigated image and the face/non-face centroids. The proposed system is composed of three major modules: Best fit plane removal unit, Histogram equalization unit, and cascaded classification unit. Comprehensive optimization...
In this work, we present architecture for real-time implementation of INTRA 4 times 4 algorithm used in H.264/AVC baseline profile video coding standard. The INTRA 4 times 4 is composed by intra prediction 4 times 4, integer transform 4 times 4, quantization 4 times 4, inverse integer transform 4 times 4, inverse quantization 4 times 4. This hardware is designed to be used as part of a complete H...
3D games use normal mapping techniques to improve the realism and visual detail of scenes when lighting models are applied. Normal map data is typically compressed to reduce the data storage requirements of a normal map image for a complex object. This paper presents a hardware implementation of a decompression algorithm for a recently proposed compression technique for normal map images. The hardware...
Address-event-representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with miliiseconds timings)...
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