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Although standard 32/64-bit arithmetic is sufficient to solve most of the scientific-computing problems, there are still problems that require higher numerical precision. Multiple-precision arithmetic (MPA) libraries are software tools for emulation of computations in a user-defined precision. However, availability of a reconfigurable cards based on field-programmable gate arrays (FPGAs) in computing...
Reconfigurable computing is rapidly establishing itself as a major discipline, involving the use of reconfigurable devices for computing purposes. This paper proposes the ORRes approach for a time-sharing of reconfigurable resources. We investigate the overlay architecture at the hardware layer to ensure the bitstream compatibility between heterogeneous FPGAs. Two novel overlay features are introduced:...
Logarithmic Number System (LNS) based multiplier plays a significant role in the fields of Digital Signal Processing (DSP), Image processing and Neural network which needs a lot of arithmetic operation. In all arithmetic operations, the multiplication is most hardware consuming component. Here, we give a possible solution to that problem by using an efficient VLSI architecture of Mitchell's algorithm...
FFT is one of the essential tools used in applications such as video processing, image processing and multi carrier systems. But due to its intensive operation, it takes more area along with increased power consumption. Hence, a hardware efficient FFT algorithm is a prime requirement. After a survey of various FFT algorithms, because of its pipeline architecture Radix-22 SDF algorithm is chosen as...
The Article concerns extension of MIPSfpga processor instruction set for acceleration of calculations related to navigation that are performed by FPGA based embedded system. Coordinate system transformation has been chosen as the reference task. Trigonometric functions calculation and multiplication operation have been chosen as acceleration targets as the most extensively used in transformation matrix...
In this paper, we describe the Heterogeneous System Architecture Foundation's application to digital signal processors (DSP) and hardware accelerators. We provide an overview of the HSA runtime, system architecture and programmer's model, identify characteristics of DSPs and compare differences in algorithms to GPUs. We show an example mapping of HSA agents to a modern DSP using the HSA intermediate...
Dataflow graphs obtained from benchmark applications depend on the compiler used and its settings. This makes comparison of results in high level synthesis research using such dataflow graphs difficult. Therefore, a synthetic dataflow graph generator for generating dataflow graphs of any size from a few tens of nodes to thousands of nodes for research in high level synthesis is presented. The user...
Lately it has been argued that standard architectures as modern x86 can outperform classic Digital Signal Processors in the embedded domain. X86 started to include some classical DSP features and have greater support for I/O, file access, extended memory etc. However, even those studies showed that it depends on the characteristics of the targeted domains. Specific algorithms (echo canceling etc)...
The increase in performance and internal memory of current DSP cores allows most applications to have software only implementations. However, recent applications in telecommunications (e.g. MPEG-4) require more and more computational power. A solution to this problem is to implement a subset of the algorithm in hardware. In this paper we present a software only and a mixed hardware/software solution...
Targeting the rapid development, with reduced complexity, of power converters control techniques, a field-programmable gate array (FPGA) based platform is proposed. The aim of the platform is to provide an effective support to the developer in the error-prone process associated to a traditional FPGA design flow. This work also enables remote hardware reconfiguration, and networking monitoring of power...
Digital Signal Processors (DSPs) have shown the great strengths in digital signal processing algorithms such as digital filtering and Fourier analysis. This work is about an implementation for a specific computational unit based on the proposed RISC instruction set architecture (ISA) of 32-bit VLIW Fixed-point DSP processor core presented in our previous work. The computational unit is designed to...
The design of spectrum monitoring receiver usually uses such a hardware model being consist of FPGA (Field Programmable Gate Arrays) and DSP (Digital Signal Processor) mainly, which requires the baseband datas and spectral datas under different bandwidths can be real-time transmitted between the FPGA and DSP. In this paper, according to the characteristics of the receiver, by using the ability, processing...
Multiplier-accumulator is a specific hardware unit that performs a common operation - computing the product of two numbers and adding that product to an accumulator. Especially, in digital signal processing applications which consist of a large number of convolution operations, the emergence of MAC unit contributes greatly to the high performance of the systems. This work is about an implementation...
This paper describes a flexible hardware and software architecture that is simple, works with almost all Software Defined Radios (SDR) in market today and is vendor independent in its implementation. Usually, an engineer targets a particular platform which needs considerable time and manpower for process of design and development. The proposed architecture can be applied almost exclusively to the...
In order to meet the requirements of wireless image transmission system, an interface was designed for external memory interface(EMIF) of TMS320DM365 and FPGA. Firstly, their hardware connection was given, and a stable pin is used as interrupt signal. Then the EMIF device driver under embedded Linux system was described in detail. The working process in both transmission and receiving FPGA were introduced...
This paper presents an architectural technique to efficiently implement multi-stage additions through operand segmentation. Carry bypass is leveraged to break the dependency between the two segmented adders, reducing the delay of the critical path. This allows for power- and area-efficient hardware implementation due to the increased timing margin for architectural transformations at the cost of one...
Combined TMS320C6455DSP and FPGA data acquisition platform, this paper describes the C6455 DSP Enhanced Direct Memory Access (EDMA) hardware architecture and configuration methods, focusing on the EDMA applied in two ways, both of which increase the transmission DSP data transfer speed, enhanced the DSP processing power to meet the physical layer of TD-LTEA complex algorithms in real time operations...
This paper introduces the structure of Embedded image collection and display system, proposes the implementation of system, structures image collection and display system by BF533 and MT9V111, collects the image by CMOS Sensor and displays the image on LCD. The paper introduces hardware interface and equipment performance of EBF533 and MT9V111, prepares control function and display function. The paper...
An algorithm which minimizes the hardware resources of fixed-point operations for a given accuracy is presented. For range analysis, forward propagation is used in order to determine the ranges of the intermediate signals. For the precision analysis, a search algorithm is used. Analytical quantization error models are used with the precision search algorithm. The main novelty of this work is the use...
Preemption techniques for hardware (HW) tasks have been studied in order to improve system responsiveness at the task level and improve utilization of the FPGA area. This letter presents a fair comparison of existing state-of-the-art preemption approaches from the point of view of their capabilities and limitations as well as impact on static and dynamic properties of the task. In comparison, we use...
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