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Logarithm and exponential functions are frequently used in signal processing, communication and information theory. They are primarily used for hardware calculations, handling multiplications, divisions, powers, and roots effectively. This paper presents a ROM based approach for the evaluation of base-2 logarithm and exponential at single precision floating point input. Since the method used is non-iterative,...
In this paper we present the design and implementation of TMbox: An MPSoC built to explore trade-offs in multicore design space and to evaluate parallel programming proposals such as Transactional Memory (TM). Our flexible system, comprised of MIPS R3000-compatible cores is easily modifiable to study different architecture, library and operating system extensions. For this paper we evaluate a 16-core...
Coarse Grained Reconfigurable Arrays (CGRAs) are typically very efficient for a single task. However all functional units are required to perform in lock step, wasting resources and making complex programming flows difficult. Massively Parallel Processor Arrays (MPPAs) excel at executing unrelated tasks simultaneously, but limit the amount of resources dedicated to a single task. We propose an architecture...
Problems involving network design can be found in many real world applications such as power systems, vehicle routing, telecommunication networks, phylogenetic trees, among others. These problems involve thousands or millions of input variables and often need information and solution in real time. In general, they are computationally complex (NP-Hard). In this context, metaheuristics like evolutionary...
Self-healing systems can restore their original functionality by use of run-time self-reconfiguration, a feature supplied by state of the art FPGA devices. Commonly, integrity checks are performed by reading back the device configuration and validating its hash value. Systems which are prone to tampering and piracy of intellectual property may disable configuration readback, which renders this method...
Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide different perspectives of a design, many require that the design be fully re-implemented for parameter modifications or do not allow the design to be run at full-speed. Designs are frequently first modeled using a high-level language then later...
FPGAs have been improved significantly in terms of performance and capacity over the last 20 years. The scale of FPGA based design also sparked off the demands for high-level synthesis to handle complicated applications. A well known intricate application is the FMM (Fast Multipole Method) algorithm of N-body problem, which is so complicated that it was not implemented on FPGA as reported in literature...
This study analyses and compares the most popular Montgomery multiplication algorithms for their power dissipation on FPGA devices. Among various architectures proposed for Montgomery multiplication, we pick the parallel, sequential and systolic variants as the most revealing ones for our experimental needs. The synthesis results indicate that the sequential setting with a single cell gives the most...
Currently few architectural approaches propose new paths to raise the performance of conventional sequential instruction streams in the time of the billions transistor era. Many application programs could profit from processors that are able to speed up the execution of sequential applications beyond the performance of current super scalar processors. The Grid Alu Processor (GAP) is a runtime reconfigurable...
Hardware binding is a crucial step in high-level synthesis. In this paper we propose a path based hardware binding algorithm to create area-time efficient designs. The algorithm performs simultaneous FU and register binding based on weighted and ordered compatibility graphs. The proposed algorithm tries to reduce interconnects in the design by exploiting flow dependencies in the DFG, leading to area...
The newest generation of sequencing instruments, such as Illumina/Solexa Genome Analyzer and ABI SOLiD, can generate hundreds of millions of short DNA “reads” from a single run. These reads must be matched against a reference genome to identify their original location. Due to sequencing errors or variations in the sequenced genome, the matching procedure must allow a variable but limited number of...
Unlike traditional SoC (System-on-chip) chip, multiprocessor chip that contains multiple independent processors, each processor owns different applications, so we need to make a reasonable multiprocessor chip initialization program. This paper proposes a design for the multiprocessor system initialization. The main contribution is as follows: Firstly, one method for the implementation of multiprocessor...
Clock gating and operand isolation are two techniques to reduce the power consumption in state-of-the-art hardware designs. Both approaches basically follow a two-step procedure: first, they statically analyze a hardware circuit to determine irrelevant computations. Second, all parts which are responsible for these computations are replaced by others that consume less power in the average case, either...
This Traditional UART IP hard core is poor at flexibility and transportability while UART IP soft core is only based on poll and interrupt mode at present which consumes so much time of CPU that the performance of embedded system is reduced greatly. UART IP soft core based on DMA mode is proposed and well elaborated using the characteristic of DMA. The IP core is AVALON bus-compatible with the control...
With the increasing chip density and the continuous improvement of reliability requirements, the concurrent error detection techniques in register transfer level have become an increasing concern. Because of the actual low probability of failure occurring, a number of semi-concurrent error detection techniques are feasible. The circuits can be checked in every N iterations. So the recomputations will...
The coupling architecture containing an FPGA device and a microprocessor has been widely used to accelerate microprocessor execution. Therefore, there have been intensive researches about synthesizing high-level programming languages (HLL) such as C and C++ into HW in the high-level synthesis community in order to make the work of reconfiguring the FPGA easier. However, the difference in a calling...
Traditional frequency measurement based on MCU is benefit from its low-cost, however, disadvantage which includes low precision and narrow frequency range also exist in this kind of system. This paper demonstrates a project which combines FPGA with MCU, fully exert the high speed property of FPGA, the easy-calculate quality and flexible control of peripheral of MCU, using method of equal precision...
The plan to design hardware real-time operating system based on FPGA is presented and the harden of the μC/OS-II is done, in order to resolve the problem that the real-time operating system kernel takes a lot of system resources and reduces the schedulability of application. The major function module of RTOS is composed of four parts the management of the event flag group (EFG), the semaphore management,...
SIMD devices have gained widespread acceptance in modern microprocessor designs for their superior performance for multimedia applications. However, there are three remaining limitations to the efficient utilization of SIMD devices in general-purpose computer systems: memory alignment, data reorganization and control flow. This paper presents SIF, an efficient SIMD interface framework that addresses...
Due to increases in design complexity, routing a reset signal to all registers is becoming more difficult. One way to solve this problem is to reset only certain registers and rely on a software initialization sequence to reset other registers. This approach, however, may allow unknown values (also called X-values) in uninitialized registers to leak to other registers, leaving the design in a nondeterministic...
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