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Due to the dramatic increase in design complexity, verifying the functional correctness of a circuit is becoming more difficult. Therefore, bugs may escape all verification efforts and be detected after tape-out. While most existing solutions focus on fixing the problem on the hardware, in this work we propose a different methodology that tries to generate constraints which can be used to mask the...
Using Si/SiGe CMP in the emitter module of SiGe:C HBT fabrication is an innovative approach in two respects. First, it allows one to simplify the fabrication process, enabling real low-cost HBT modules. Second, it can also be applied to form a fully self-aligned HBT structure, enabling highest RF performance. In this paper, we focus on CMP process optimization. We will show that a previous disadvantage...
In this paper, we discuss a method to extrapolate intrinsic and extrinsic Ron components for a JFET. The results provide the guideline to lower Ron, hence to achieve competitive “Ron vs. pinch off (Voff)” benchmark. The optimization impacts on channel length scaling and process variation are discussed. Besides, an improved RESURF condition is achieved using one of the experimental conditions. The...
This paper details a new 14V Complementary BiCMOS (CBiCMOS) addition to the TowerJazz SBC35 family of BiCMOS technologies. The SBC35 family previously supported BVceo values up to 6V. The bipolar architecture is nearly identical with that used in the lower voltage technologies, leveraging 10 years of manufacturing history. The complementary bipolar transistors are paired with 5V CMOS currently available...
With the challenges of growing functionality and scaling chip size, the possible performance improvements should be considered in the earlier IC design stages, which gives more freedom to the later optimization. Potential slack as an effective metric of possible performance improvements is considered in this work which, as far as we known, is the first work that maximizes the potential slack by retiming...
The application of soft-switching concepts or silicon carbide (SiC) devices are two enabling technologies to further push the efficiency, power density or specific weight of power electronics converters. For an automotive application, such as a DC-DC converter that interconnects the high voltage battery or ultra-capacitor in a hybrid electrical vehicle (HEV) or a fuel cell vehicle (FCV) to the DC-link,...
Reliable design of power distribution network for stacked integrated circuits introduces new challenges i.e., substrate coupling among through silicon vias (TSVs) and tiers grid in addition to reliability issues such as electromigration and thermo-mechanical stress, compared to conventional system on chip (SoC). In this paper a comprehensive modeling of the TSV and stacked power grid with frequency...
This brief paper deals with using the particle swarm optimization metaheuristic for optimally sizing switched current (SI) memory cells, namely the class AB grounded gate SI memory cell. Pareto front is generated while optimizing two main conflicting performances: maximizing both the signal to noise ratio and the sampling frequency. SPICE simulation results are presented to validate obtained sizing.
Basic film step coverage and gap-fill data has been consolidated and compared with the observed thin film CVD kinetics trends. Based on some assumptions regarding reaction kinetics, obtained correlations are believed to be applicable for an optimization of ultra small gap filling in deep submicron integrated circuit technology.
Networks-on-Chip (NoC) is the promising communication architecture for next generation SoC. The buffer size of on-chip router impacts the silicon area and power consumption dominantly. Optimizing the buffer usage is important for an efficient NoC design. In this paper, we propose an buffer optimization algorithm for application-specific NoC design. More precisely, given the application traffic parameters...
Gate misalignment and process variations are important challenges in sub-20 nm gate length planar double-gate (DG) MOSFET devices. For the first time, we demonstrate a misalignment- and process variations-aware device optimization strategy for a DG-MOSFET. Using underlaps and high-kappa offset-spacers, we show that the robustness of the device to gate misalignment and process variations can be improved...
Sizing of analog circuits requires the consideration of both continuous and discrete design parameters, e.g. due to predefined manufacturing grids. In this paper, a new method is presented to solve this task. It is based on an iterative optimization process with random-based searches on search regions that are determined by performance gradients. Experimental simulation results of operational amplifiers...
Fluorine plasma ion implantation is a robust technique that enables shallow implantation of fluorine ions into group III-nitride epitaxial structures. This technique has been used to achieve robust threshold control of the AlGaN/GaN high electron mobility transistors (HEMTs) and led to the realization of self-aligned enhancement-mode devices. To reveal the atomic scale interactions and provide a modeling...
As technology is aggressively scaled, nano-regime VLSI designs are becoming increasingly susceptible to process variations. Unlike pre-silicon optimization, post-silicon techniques can tune the individual die to better meet the power-delay constraints. This paper proposes a variation-aware methodology for the simultaneous gate sizing and clustering for post-silicon tuning with adaptive body biasing...
The reliability against transient faults poses a significant challenge due to technology scaling trends. Several circuit optimization techniques have been proposed in the literature for preventing soft errors in logic circuits. However, most approaches do not incorporate the effects of other design metrics like delay and power while optimizing the circuit for soft error protection. In this work, we...
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