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Unique defect related to the tighter process margins on STI HDP process was investigated. The root cause was Si surface damage due to smaller top width of HDP. The defect was improved by HDP deposition process optimization derived relationship between ion incident angle and sputtering rate during deposition process. It was elucidated that HDP process is important for not only gap filling capability...
A PI controller is one of the most widespread controller types used in industry. If the structure and order of a controller is restricted (e.g. a PI controller as is the case in this paper), this may cause worse output variance as compared to the minimum variance (MV) benchmark. Finding the best achievable performance boundary for this controller is a challenging task as it leads to a non-convex optimization...
Wafer Level Package (WLP) is one type of advanced package with a rapid growth and wide applications in many consumer electronic markets. However, it is different from conventional assembly that after wafer probing, there is no final electrical test to identify the defects produced by WLP Die Processing Service (DPS). This paper focused on three key processes of DPS which are backside grinding, wafer...
This paper deals with the problem of nonlinear model predictive control using a piecewise linear predictive model: the adaptive hinging hyperplanes (AHH). The AHH model is adaptive and efficient, thus depicts the relationship of the nonlinear system very well. Thanks to the piecewise linear property of the predictive model, a series of convex quadratic programming are constructed in the controller...
We present a systematic process control procedure that enables an integrated process optimization of wet chemical cleaning and subsequent thermal oxidation processes. Our approach uses distinct experiments to reveal the impact of individual parameters on the effective minority carrier lifetime. Special focus is put on an application in a production line. Therefore, both wet-chemical processing and...
Control structure design deals with the selection of controlled and manipulated variables, and the pairings interconnecting these variables. The available criteria for these tasks require enumeration of every alternative, which can be computationally forbidding for large-scale process. Owing to the computational complexity, variables and pairings are often selected sequentially, which may result in...
We report on a 65 nm Ge pFET with a record performance of Ion = 478muA/mum and Ioff,s= 37nA/mum @Vdd= -1V. These improvements are quantified and understood with respect to halo/extension implants, minimizing series resistance and gate stack engineering. A better control of Ge in-diffusion using a low-temperature epi-silicon passivation process allows achieving 1nm EOT Ge-pFET with increased performance.
In the work is formalized the problem of sustainable development of production, i.e. the optimum choice of parameter values of technological process with the purpose of minimization of the risk of obtaining the production of unplanned quality and of making incorrect decision about the quality of production and maximization of production profit at the guaranteed social and economic effects. Different...
This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mode that is strongly supply-voltage dependent and also introduce a simple yet novel method for quantifying the effects of process variability on digital timing - a delay overlapping stage...
For several decades, the output from semiconductor manufacturers has been high volume products with process optimisation being continued throughout the lifetime of the product to ensure a satisfactory yield. However, product lifetimes are continually shrinking to keep pace with market demands. Furthermore there is an increase in dasiafoundrypsila business where product volumes are low; consequently...
The challenges of deriving early-adopter competitive advantage, even with fabless access to process technology, through leveraging features offered by the advanced, and possibly disruptive, process technologies in real SoC products, are outlined. A structured methodology for addressing these challenges, and bridging the gap between process and design, sufficiently early in the development cycle to...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
Multi-core SoC created great opportunities to increase overall system performance while keeping the power in check but also created many design challenges that designers must now overcome. The challenge of doubling performance every two years used to drive superscalar design with more functional units running concurrently or deeper pipeline racing for highest frequency at the cost of higher power...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
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