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SIMD (Single Instruction Multiple Data) extension units are ubiquitous in modern processors. Array indirections raise several challenges for SIMD vectorization including disjoint memory access, unknown alignment and dependence cycle. Existing SIMD automatic vectorization methods fail to handle these challenges very well. This paper presents a new method exploiting Pure SLP (Superword Level Parallelism)...
Taint-based Concolic testing is a software testing technique, which combines dynamic taint analysis, symbolic testing and concrete execution. Concolic testing is faster than symbolic testing while maintaining the same precision. Taint-based concolic testing uses dynamic taint analysis to help identify instructions related to inputs, and at the same time reduce the total number of constraints. Although...
Buffer overflow vulnerabilities are currently the most prevalent security vulnerability. The paper presents a method that combines static analysis with dynamic test to deal with the problem on buffer overflow vulnerabilities detecting. By using the method we can identify potential weakness locations. A buffer overflow vulnerabilities testing system was developed. The experiment results tested and...
The paper highlights the need to apply the test-per-clock method at full clock rates to test crosstalks in networks of long interconnections between modules in a System on a Chip (SoC). The proposed method of testing n-interconnects involves the 3n-R-LFSR (Ring Linear Feedback Shift Register) with a polynomial that guarantees the long counting cycle. The part of the ring LFSR that generates test patterns...
A new lossy compression algorithm for RF ultrasound signals (A-scan) is presented, which stores only the largest variations of the original signal. The largest variation (LAVA) algorithm is a two-step, constant bit-rate (CBR) algorithm, using only simple addition/subtraction operations, which is very suitable for FPGA implementation. The algorithm is targeted for automated ultrasonic testing (AUT)...
Cryptographic devices are recently implemented with different countermeasures against side channel attacks and fault analysis. Moreover, some usual testing techniques, such as scan chains, are not allowed or restricted for security requirements. In this paper, we analyze the impact that error detecting schemes have on the testability of an implementation of the advanced encryption standard, in particular...
Software-based self-test (SBST) is increasingly used for testing processor cores embedded in SoCs, mainly because it allows at-speed, low-cost testing, while requiring limited (if any) hardware modifications to the original design. However, the method requires effective techniques for generating suitable test programs and for monitoring the results. In the case of processor core testing, a particularly...
The downsizing of transistor dimensions enabled in the future nanotechnologies will inevitably increase the number of faults in the complex ULSI chips. To maintain the production yield at acceptable level, several levels of protection mechanisms will have to be implemented to tolerate the permanent and transient faults occurring in the physical layers. In this paper, we study fault tolerance at the...
Feature matching is a difficult and key problem of the feature-based image registration methods. A new algorithm based on feature similarity is proposed in this paper to deal with the correspondence of features. It mainly consists of three steps: first, a candidate matched feature pairs set is obtained using feature similarity which is computed by the invariant descriptors of features extracted from...
Transient Response Analysis [1] (TRA) is a quick and inexpensive method of testing analogue circuitry. In this paper we compare the effectiveness of traditional DC testing of analogue circuit cells with dynamic tests, using a simple analogue subcircuit element which models one component of a large mixed-signal ASIC.
A formal framework is presented in which to explore the complexity issues of data structures which accommodate various types of range queries. Within this framework, a systematic and reasonably tractable method for assessing inherent complexity is developed. Included among the interesting results are the following: the fact that non-linear lower bounds are readily accessible, and the existence of...
Many machines can be decomposed into a linear cascade of identical sequential machines. We consider the problem of implementing fault detection experiments for such machines. Cascade equivalence and information lossless properties of cascade machines are studied. Sufficient conditions for efficient testing of these machines are derived. Procedures are presented for testing cascades of arbitrary length...
This report describes the techniques used to obtain two three-variable universal logic blocks from NAND circuits. The emphasis for one of these ULB's is on minimizing NAND blocks; for the other ULB, it is on minimizing input pins. The techniques used for the three variable ULB realization are extended to handle realization of a four-variable ULB. Possible compromises to be made in the ULB approach...
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