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We propose the first optical SDN model enabling performance optimization and comparison of heterogeneous SDN scenarios. We exploit it to minimize latency and compare cost for non-SDN, partial-SDN and full-SDN variants of the same network.
This paper introduces new capability on System on a Chip (SoC) ATE, called "Functional Test Abstraction (FTA)", which allows us to execute an automatically generated system level functional test program from the system level design verification environment. The device under verification and device under test can be a complex SoC which has multiple logic time domains and multiple interfaces...
We propose Proximity-Aware cache Replication (PAR), an LLC replication technique that elegantly integrates an intelligent cache replication placement mechanism and a hierarchical directory-based coherence protocol into one cost-effective and scalable design. PAR dynamically allocates replicas of either shared or private data to a few predefined and fixed locations that are calculated at chip design...
Current hardware implementations of TLS (thread-level speculation) in both Hydra and Renau's SESC simulator use a global component to check data dependence violations, e.g. L2 Cache or hardware list. Frequent memory accesses cause global component bottlenecks. Implementation and verification of the global component dramatically slows the processor's frequency. In this paper, we propose a cache coherence...
Multidestination communications are a highly necessary capability for many coherence protocols in order to minimize on-chip hit latency. Although CMPs share this necessity, up to now few suitable proposals have been developed. The combination of resource scarcity and the common idea that multicast support requires a substantial amount of extra resources is responsible for this situation. In this work,...
Hardware implementations of Internet Protocol (IP) classification algorithms have been proposed by the research community over the years to realize high speed routers and Internet backbone. Decomposition-based IP classification algorithms are desirable for hardware implementation due to their parallel search on multiple fields. These algorithms consist of two phases: independent searches on each packet...
Low-cost Radio Frequency IDentification (RFID) tags are extremely resource-constrained devices, therefore, difficult to defend against corruption attacks. Meanwhile, forward privacy considers how to preserve the privacy of compromised tags. The majority of existing authentication protocols uses cryptographic hash functions to preserve forward privacy under the random oracle model, but the expensive...
To meet the demand for more powerful high-performance shared-memory servers, multiprocessor systems must incorporate efficient and scalable cache coherence protocols, such as those based on directory caches. However, the limited directory cache size of the increasingly larger systems may cause frequent evictions of directory entries and, consequently, invalidations of cached blocks, which severely...
This paper compares the decomposition, integration, and transformation methods used in mathematics, electronic design and software developing, reaching the essence of each method. Decomposition need to concern about orthogonality of the separated result pieces. There should be deeper and wider use of those universal methods in software design.
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