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This paper proposes an adaptive method to modify network delay caused by clock skew. First, we introduce the concept of end-to-end network delay, and then we propose a method which aims at eliminate the effect cause by the difference clock frequency. The method first denoises the data set to remove error points, and then uses Least Square Method to estimate the clock skew in distributed network. Finally,...
Currently in deep sub-micron technologies such as 16 nm and smaller, requirement of portable devices focus designers' attention on low power design of CMOS circuits and systems, using different low power techniques, trying to decrease dynamic and/or leakage power. One of the widely employed power optimization methods is multi voltage design, used to reduce power by dividing IC into voltage IC domains...
Time mode signal processing (TMSP) is the implementation of analog signal processing functions using the most basic element available, namely, propagation delay. Moreover, a time to digital converter (TDC), an important block of time mode circuits, could be used to convert the time difference between two edges of two signals into a sequence of digital numbers. In this paper, a new time mode SerDes...
This research describes an approach to test metastability of flip-flops with help of multiple at speed capture cycles during path delay test. K longest paths starting from a flip-flop are generated, such that a long path on one clock cycle feeds a long path on the next clock cycle, and so on. This permits the testing of flip-flop metastability and time-borrowing latches, that cannot be tested by any...
Adders are the basic building blocks of any processor or data path application. In adder design carry generation is the critical path. To reduce the power consumption of data path we need to reduce Area and number of transistors of the adder. Carry Select Adder is one of the fast adder used in many data path applications. In this paper Power consumption, area and delay of different carry select adders...
Clock skew minimization is an important topic in the design of synchronous sequential circuit. As the process technology scaling, the effect of process/voltage/temperature (PVT) variations on clock skew has become a serious concern. It is known that, during the post-silicon stage, adjustable delay buffers (ADBs) can be utilized to eliminate the clock skew. However, unless ADBs have a self-adjusting...
The Advanced On-Chip Variation (AOCV) model is used to systematically correct Liberty timing file for on-chip variation (OCV) based on the logic depth and distance of a path. The AOCV analysis solutions can be categorized into graph-based (GBA) and path-based analysis (PBA), which are refinement strategies over traditional OCV in static timing analysis. PBA AOCV performs recalculation on critical...
Orthogonal Frequency Division Multiplexing (OFDM) has achieved substantial attention in the past couple of the years. In our contemporary world the need for quicker data transmission is not at all-ending. OFDM modulation technique gives us with a way of more thickly packing modulated carriers in the frequency domain than other Frequency Multiplexing methods, thus attaining higher data rates through...
This paper investigates the clock synchronization problem for Device-to-Device (D2D) communication without infrastructure. Employing affine models for local clocks, it is proposed a random broadcast based distributed consensus clock synchronization algorithm. In the absence of transmission delays, we theoretically prove the convergence of the proposed scheme, which is further illustrated by the numerical...
Branch prediction is crucial to maintaining high performance in modern superscalar processor. Today's superscalar processors achieve high performance by executing multiple independent instructions in parallel. One of the most impedement to the performance of wide-issue superscalar processor is the presence of conditional branches. Conditional branches can occur as frequently as one in every 5 or 6...
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