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We consider the problem of proactive (i.e. predictive) content caching that is aware of the costs of retention of the content in the cache. Prior work on caching (whether proactive or reactive) does not explicitly take into account the storage cost due to the duration of time for which a content is cached. This new problem, which we call retention aware caching, is motivated by two recent technological...
Orthogonal frequency division multiple access is a technique in which single data stream is transmitted with small rate of subcarriers. OFDM system needs FFT processor for generation of subcarriers. A Radix-2 Based 32 bit and 64 Point Pipeline FFT Processor Using bit parallel multiplication process for OFDM system is presented in this paper. Proposed architecture uses single path delay feedback FFT...
FFT is a crucial and necessary design entity lor any current communication applications, especially for OFDM systems. As compared with conventional design approach, which can support only one-radix processing kernel of single-path delay feedback (SDF) FFT, we propose a reconfigurable processing kernel design for multiple-radix types of SDF FFT. In implementation, this kernel hardware engine is reconfigurable...
Today, the transition of traditional networking model to SDN-type architectures poses several major challenges. In typical SDN settings, the routers and switches frequently generate requests to the controller which ensures the proper and efficient operation of the network. Increased workload on the controller results in larger control plane response times, which, in turn, leads to a delayed response...
High sampling rate Analog-to-Digital Converters (ADCs) can be obtained by time-interleaving low rate (and thus low cost) ADCs into so-called Time-Interleaved ADCs (TI-ADCs). Nevertheless increasing the sampling frequency involves an increasing sensibility of the system to desynchronization between the different ADCs that leads to time-skew errors, impacting the system with non linear distortions....
This paper presents the design and hardware implementation of two-stage lumped-element All-Pass Network for group delay engineering. It is designed for 700 MHz band that is assigned for Software Defined Radio and Cognitive Radio applications. Both positive and negative group delay variation is obtained across the band with slope +5.3 ns/GHz and −4.7 ns/GHz. The application of real-time frequency discriminator...
The manifestation of radix2 was a highlight in the design of efficient FFT hardware architectures. Afterward, radix2 was extended to R2MDC and R2SDF However, radix2 was only planned for (SDF) single-path delay feedback structures, other than not intended for feed-forward ones, also called (MDC) multi-path delay Commutator. In this paper, the design of R2MDC (Radix2 Multipath Delay Commutator and R2SDF...
Many power-aware resource allocation problems in packet networks can be modeled as single-server queueing systems, in which the power consumption depends on the actual service rate. We consider the scenario in which the queue service rate is controlled to minimize server power consumption. We show that power control methods that tune the service rate by using the queue length or the arrival rate exhibit...
We present the analytical model and the electrical characterization of a controllable delay component for a micropipeline architecture suitable for being designed with a semicustom design approach. An interesting feature of the component is that it is lockable, i.e., it can be controlled in an on/off fashion, permitting synchronous operation for testing purposes by means of an opportune architecture...
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