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The problem of increasing the coefficient of technical readiness of memory module, the value of which increases with decreasing of control system recovery time in case of failure of its constituent units, is solved. The proposed structure of the memory module with built-in self-test and restore functionality that will allow auto-replacing bits of data of the main memory cell array, in which there...
Embedded microprocessor cache memories suffer from limited observability and controllability creating problems during in-system tests. This paper presents a procedure to transform traditional march tests into software-based self-test programs for set-associative cache memories with LRU replacement. Among all the different cache blocks in a microprocessor, testing instruction caches represents a major...
This paper proposes a programmable Built-In Self-Test (BIST) approach for DRAM test and diagnosis. The proposed architecture suits well for embedded core testing as well as for stacked and stand-alone DRAMs and it provides programmability features for executing both March and NPSF-oriented test algorithms. The proposed BIST structure is designed to be easily customized with memory topology parameters...
Considering the physical layout, a comprehensive TCAM test scheme divides TCAM test into test for TCAM core and test for peripheral circuit. Besides, it schedules the existing test algorithms to develop an optimized test algorithm.
Dynamic cache resizing coupled with built in self test (BIST) is proposed to enhance yield of SRAM-based cache memory. BIST is used as part of the power-up sequence to identify the faulty memory addresses. Logic is added to prevent access to the identified locations, effectively reducing the cache size. Cache resizing approach can solve for as many faulty locations as the end user would like, while...
Testable design techniques for systolic motion estimators based on M-testability conditions are proposed in this paper. The whole motion estimator can be viewed as a two-dimensional iterativelogicarray (ILA) of processing elements (PEs) and multiplying elements (MULs). The functions of each processing element and multiplying elements are modified to be bijective to meet the M-testable conditions...
Software-based self-test (SBST) is increasingly used for testing processor cores embedded in SoCs, mainly because it allows at-speed, low-cost testing, while requiring limited (if any) hardware modifications to the original design. However, the method requires effective techniques for generating suitable test programs and for monitoring the results. In the case of processor core testing, a particularly...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
The Niagara2 CMT system-on-chip incorporates many design-for-test features to achieve high test coverage for both arrays and logic. All the arrays are tested using memory built-in-self-test. This is supplemented with scan-based testing. Logic is tested with standard ATPG for slow-speed defects and extensive use of transition test, along with logic built-in-self-test for the SPARC cores, for at-speed...
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