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In this paper we present an implementation of the asynchronous/synchronous processor array (ASPA2) - a digital SIMD vision chip. The chip has been fabricated in a 0.18 μm CMOS process and comprises 80×80 array of pixel processors. The architecture of the chip is overviewed, the design of the processing cell is presented and implementation issues are discussed. At 75 MHz ASPA2 demonstrates 373 GOPS/W...
A novel multi-rate Time-Interleaved Current Steering Digital to Analog Converter with unity element sharing is presented. Proposed 12-bit DAC is simulated in 90nm CMOS technology. The implemented DAC is divided to two segments, MSB and LSB segments, each having 6 bits of resolution. Taking advantage of the oversampling requirement due to the reconstruction filter at the DAC output, the MSB segment...
Emerging 3D-integration enables integrating high quality image sensors with various massively parallel processing elements. Analog motion estimation is one potential application, which is likely to result in significant benefits in the form of low power or high frame-rate 3D-integrated image sensor-processors. The system-level operation of a proposed analog motion estimation array, enabling all various...
The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic architectures. The novel FPGA structure is based on the combination of CMOL (Cmos + MOLecular scale devices) FPGA circuits and recent improvements and generalization of the CMOL concept to allow multilayer crossbar integration, compatibility...
Reconfigurable mixed grain architectures have been demonstrated to be efficient and flexible for data parallel and computation-intensive applications. In this paper we present the design of a new Reconfigurable Cell (RC) based on a mixed-grain architecture. The architecture delivers a gate-level implementation of the Reconfigurable Logic Unit (RLU) focusing on the ALU implementation. The investigation...
This paper presents the MIPA4k, a 64times64 cell mixed-mode image processor array chip. The processor cell includes an image sensor, A/D/A conversion, embedded digital and analog memories and hardware-optimized grayscale and binary processing cores. This paper presents the architecture of the processor cell and the different functional hardware. The processor has been manufactured in a 0.13 micron...
This paper presents an SRAM architecture employing a multiword-based ECC (MECC) scheme for soft error mitigation and a row virtual ground technique for array leakage reduction. The MECC combines four data words to form a 128 bit composite ECC word, two of which are interleaved in a row to mitigate cosmic neutron-induced multi-bit errors. The use of a composite word reduces the number of check-bits...
This paper reports a functional 4F2 DRAM based on a vertical-channel-access-transistor (VCAT). A new core design methodology is applied to accommodate 4F2 cell array, achieving both high performance and small area. The 88Kb DRAM array is fabricated in a 50Mb test chip at 80nm design rule and the measured random cycle time (tRC) and read latency (tRCD) is 31ns and 8ns, respectively. The core array...
A microelectronic chip for the ultra-rapid detection of cells in few micro-liters drop samples is presented. The architecture is based on a two-dimentional 640times480 array of microsites. Dielectrophoresis (DEP) is the physical phenomenon used to manipulate the cells. A corresponding array of photodiodes is used for integrated optical detection. The chip implements a column-parallel, reconfigurable...
This paper presents a PIM-based (Processing-in-Memory) architecture based on new reconfigurable cell data path. The architecture delivers increased power/throughput/area efficiency compared to previous well-known architectures. The investigation of the new reconfigurable cell design was performed in 0.18 and 0.13 micron CMOS technology nodes. Specifications of individual blocks are presented as well...
The reliability of advanced embedded non-volatile memories has been discussed using the 2T-FNFN devices example. The write/erase endurance and the data retention are the most important reliability parameters. The intrinsic reliability mechanisms can be addressed through single cell evaluation, while the cell-to-cell variation determines the product level reliability. The cell-to-cell variation can...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
A novel SRAM architecture with a high density cell in low supply voltage operation is proposed. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 um2 cell in 65 nm CMOS technology demonstrated 0...
This paper presents a programmable interconnection network for a novel multi-reticle integrated circuit providing a reconfigurable circuit board for rapid system prototyping. This multi-dimensional mesh grid network, called WaferNettrade, can actively interconnect any pair of pins of integrated circuits deposited on the configurable system board. Two crossbar architectures are implemented and compared,...
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