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In this paper the effect of on-air-combining on the signal quality in distributed transmitter systems like active antennas is described. Active antennas containing a multitude of parallel, independent transmitter chains are emerging in the mobile communication base station market. Due to the independent transmitter chains, each signal is subject to different distortions by the various transmitter...
A 14-bit 100MS/s self-calibrated Digital-to-Analog converter (DAC) is presented. Analog background self-calibration technique with a randomized calibration-period is adopted to improve the dynamic performance. The DAC is fabricated in SMIC 0.13-μm CMOS process and occupies a 1.29mm2 die area. The measured DNL/INL is better than 3.1LSB/4.3LSB. The SFDR is 72.8dB at 1MHz signal and 100MHz sampling frequency...
A 12-bit current-steering self-calibrated digital-to-analog converter (DAC) is presented. Mismatches among the current sources are compensated by the calibration scheme, so that the DAC linearity is ensured and the active area is small at the same time. This digital-to-analog data converter was implemented in a 0.18μm CMOS process, and the active area is smaller than 0.8 mm2. After calibration, the...
A voltage feedback charge-cancellation technique is proposed which prevents the conversion nonlinearity due to the parasitic effect of split DAC architecture in Successive Approximation Register (SAR) ADCs. A voltage feedback network operating as a capacitive charge-pump can efficiently detect and compensate the voltage error in each bit cycling, thus the conversion accuracy can be significantly improved...
Attaining high matching property of the current sources is very important for the design of high-speed high-accuracy current-steering DACs. This paper presents a novel calibration technique-complete-folding, which achieves the high matching accuracy by selectively regrouping current sources into a fully binary-weighted array based on the current comparisons after chip fabrication. The implementation...
In this study, the digital static calibration technique used for 400MSPS, 16-bit high-resolution current steering DAC is described. The technique uses address generator, comparator, SAR register, and calibration DAC to comprise successive approximation calibration loop. With the calibration loop, the respective calibration of array units of current source can be implemented automatically one by one,...
In this study, the digital static calibration technique used for 400 MSPS, 16-bit high-resolution current steering DAC is described. The calibration technique uses address generator, comparator, SAR register, and calibration DAC to comprise successive approximation calibration loop. With the calibration loop, the respective calibration of array units of current source can be implemented automatically...
In this paper, new sequence switching and layout techniques are presented for the design of high-speed high-accuracy current-steering DACs. Our new sequence switching technique - after-fabrication programmable switching - rearranges the switching sequence of current sources after chip fabrication, which will guarantee to generate an optimal switching sequence to achieve high static accuracy. With...
A high-performance 13 bit current-steering DAC for analog subsystems is implemented in a standard 0.13 mum CMOS technology. A novel dynamic background calibration scheme directly trims the unary DAC-elements in differently weighted segments of the current source array. Interleaved current cells implement an effective RZ- behavior with NRZ output current waveform, which improves the dynamic linearity...
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