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An ultra low voltage rail-to-rail DTMOS voltage follower is presented. The circuit is developed based on a complementary source follower with a common-source output stage. The circuit is designed using a 0.13 μm CMOS technology and SPICE is used to verify the circuit performance. The voltage follower can drive ± 0.25 V to the 500 Ω with the total harmonic distortion (THD) of 0.4% at the operating...
The paper presents a new solution to achieve rail-to-rail common mode input voltage swing for CMOS operational amplifiers. The common mode input range of a MOS differential stage is limited by the threshold voltage of the input transistors. With a pair of complementary input stages the whole range from GND to VDD can be covered. Their drain currents are summed up but the resulting current as well...
A dB-linear programmable gain amplifier (PGA)utilizing weighted input transistors, is implemented in a 0.18 μm CMOS process. The weighed input transistor units with constant current-density enable insensitive gain-steps while maintaining the load impedance condition. The gain range can cover from -18 dB to +30 dB in 6 dB steps, and the gain error is less than 1 dB. The 3 dB bandwidth (BW) is 60 MHz...
A stacked amplifier architecture has been used to achieve high RF output power levels in sub-100nm CMOS. The stacking makes it possible to both operate the power amplifier (PA) from a large supply voltage and implement RF power combining. As a proof of concept, a 6.5-GHz PA has been integrated in a 65-nm standard CMOS technology. The amplifier achieves 27.4-dBm output power with an efficiency of 19...
In this paper a current × voltage multiplier with the FVFCS is presented. This multiplier takes advantage of the very low-impedance input node of the FVFCS to sense the current signals. Additionally, uses a two cross-coupled differential pairs in order to cancel undesired components in the output current. The simulations are carried out using the standard Mixed and RF 180 nm UMC CMOS process and is...
In this paper, the use of body biasing to control gain, linearity, and noise figure in CMOS low-noise amplifiers (LNAs) is investigated. As a proof of concept, a 60-GHz 4-stage cascode CMOS variable-gain LNA is designed and laid out in a 6 5nm CMOS technology. To improve the accuracy of the post-layout simulations, all inductors are modeled and simulated with a 3-dimentional electromagnetic solver...
This paper presents the design and implementation of second generation current conveyor CCII- in 0.35μm CMOS process. In the design, we intended to achieve very low output impedance of voltage buffer over wide frequency range, in order to comply with high requirements for laboratory instrumentation. Selected approach relies on the optimization of voltage buffer, which is composed of minimal amount...
A technique for power-bandwidth scaling of a current feedback amplifier (CFA) is presented. By employing current gain, instead of the feedback resistance, to alter the closed-loop bandwidth of the CFA, the proposed approach is shown to provide 30% quiescent power savings for a bandwidth variation of 10MHz to 100MHz. Parasitic extracted simulations are performed in a 0.18μm CMOS process with a power...
In this paper we present a MOSFET-only implementation of a balun LNA. This LNA is based on the combination of a common-gate and a common-source stage with cancelling of the noise of the common-gate stage. In this circuit, we replace resistors by transistors, to reduce area and cost, and minimize the effect of process and supply variations and mismatches. In addition we obtain a higher gain for the...
A CMOS direct-conversion receiver with only one signal path is reconfigurable from 2 to 6 GHz in the RF band and from 3.6 to 54 MHz in the channel bandwidth. By employing a voltage feedback in a common-gate low-noise amplifier (LNA), the input matching of the LNA can be reconfigured for each RF band by simply changing the resonant frequency of the load network. The frequency characteristics of the...
A single-chip versatile potentiostat is presented that allows multiple amperometric electrochemical measurements at the nanoscale. Cyclic voltammetry, impedance spectroscopy, impedance time tracking and amperometry can be performed over a 1 MHz bandwidth, with sub-pA resolution and over an unlimited measuring time. The design of the current amplifier, based on a simple transistor matching architecture,...
A 1.9 GHz fully integrated Low Noise Amplifier with Partial Source Degeneration technique (LNA-PSD) has been implemented in a 0.35 ??m CMOS technology. This amplifier provides a forward gain of 11 dB with a noise figure of 3.4 dB while drawing 11 mW from a 1.8 V supply source.
A fully integrated 2 stage K-band power amplifier is designed, fabricated and measured. The amplifier is realized utilizing standard 0.18 μm CMOS process. A novel simplified matching and bias network is used in order to reduce the input and output losses and to achieve a high output power and PAE. At 24 GHz, the measured results of the amplifier are, a small-signal power gain of 16.2 dB, a maximum...
This paper presents a fully integrated V-band two stage power amplifier with cascode topology. The PA is designed on 0.25 ??m SiGe:C BiCMOS technology. The technology provides ft and fmax ?? 200 GHz. The two stage PA provides a gain of 17 dB at 64 GHz. The PA has been optimized for biasing circuit, PA Core and the matching networks. This has resulted in high power and high linearity from 58 GHz to...
A new operational floating current conveyor (OFCC) circuit is presented. The presented OFCC circuit is the first CMOS OFCC circuit which is suitable for low power VLSI applications. The proposed OFCC circuit is designed to achieve two design goals. The first designed circuit is a low power consumption OFCC circuit (LBW design) while the second design is a high bandwidth OFCC circuit (HBW design) with...
As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by vertically stacking (i.e. cascoding) transistors becomes less useful in nano-scale CMOS processes...
With the advent of miniaturised sensors for various engineering and medical applications there is an increased demand of low-power, low-voltage analog building blocks like opamps and OTAs. Degradation of certain amplifier characteristics with supply voltage is a major concern for low-voltage design and often poses contradictory requirement. CMRR (common mode rejection ratio), one such feature, is...
A new Current Feedback Amplifier (CFA) suitable for VLSI applications is presented in two different designs to serve both low power (LBW design) and high bandwidth (HBW) applications. The new circuit is employing positive current conveyor followed by amplifier followed by buffer to achieve very high trans-impedance for this CFA circuit without needing to stack many transistors together and at the...
A low noise amplifier for UWB and broadband applications is presented. The active dual loop negative feedback architecture dissevers the severe tradeoff existing between the input impedance, gain and noise figure, and produces a flat S11 across the entire band. The LNA is composed of a voltage amplifying negative feedback amplifier with a transconductance amplifier forming a shunt-shunt feedback around...
A novel low power with high performance low current comparator is proposed in this paper which comprises of low input impedance using a simple biasing method. It aimed for low power consumption and high speed designs compared with other high speed designs. The simulation results from HSPICE demonstrate the propagation delay is about 0.7 ns and the average power consumption is 130 muW for 100 nA input...
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