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In this work, a new MIN circuit for low voltage applications is presented. The approach uses a new low output impedance configuration which allows working with low power supply requirements. The circuit was simulated in PSpice and a chip prototype was fabricated and tested using CMOS AMI 0.5μm N-well technology.
This paper describes a micropower low-noise neural front-end circuit capable of recording epileptic fast ripples (FR). The front-end circuit consisting of a preamplifier followed by a 6th-order bandpass filter is designed for signal sensing in a future epileptic deep brain stimulator. A current-splitting technique is combined with an output-branch current scaling technique in a folded-cascode amplifier...
A modified regulated cascode structure that incorporate a push-pull inverting amplifier and having a low output compliance voltage is used in the implementations of proposed current mirrors. P-SPICE simulations in 0.25μm CMOS technology validate the proposed current mirror structures at 1V. They offer very high output impedance about 30GΩ, consume around 200μW of power at 100μA d.c. current, and offer...
A continuous-time delta-sigma modulator that maybe used as an interface for Electret microphones is presented. The third order modulator comprises a single-ended-to-differential-converter integrated inside the loop-filter with a single-ended high-impedance input, an RC integrator on the first stage and Gm-C integrators for the other stages. Gm-C integrators comprise highly-linear low-power transconductances...
This paper presents the design of a wide bandwidth high performance CMOS realization of dual-output second generation current conveyor (CCII±) at 32nm technology node. HSPICE simulation shows that voltage and current bandwidths in excess of 10GHz are obtained, thus making the module quite suitable for applications in the microwave range of frequencies. Besides, the circuit is able to operate at reduced...
A flipped current mirror and a flipped voltage follower suited to low-voltage and low power operation is applied to the design of current conveyors (CCII). A new topology (class-A )is proposed operating at 1.5v and featuring simplicity, compactness, low power consumption and bandwidths up to 100 MHz for a 0.5μm CMOS technology.
A modified Aska current-mode instrumentation amplifier (IA) is proposed in this paper. The main modification consists to add of a current negative impedance converter (INIC) in order to cancel the input current offset. The proposed configuration has been simulated using typical transistor parameters of the 0.35μm CMOS process from AMS. Under ±1.5V supply voltage, the circuit consumes 1.65mW. The IA...
In this paper a very low-voltage design method for a 5 GHz folded cascade topology amplifier is presented. Comparing to the conventional cascade topology our design has a better performance regarding the amplifier's power dissipation (8 mW for a 0.7 V power supply) and its high gain (20.8 dB). Circuit simulations by the use of H-Spice and a standard TSMC 0.18 um CMOS technology confirmed our design...
We propose a novel dual-mode neural stimulator circuit. For stimulation requiring small or medium amount of charge, the stimulator supplies a constant current to the stimulation load in the same way as any standard current-mode stimulator. For high-charge stimulation applications, the stimulator supplies a variable stimulus current, depending on the voltage available across the current generator circuit...
The decision for most the appropriate current mirror topology when designing a circuit is a matter of trade-offs between impedance, current transfer ratio, area on chip, power consumption and voltage-headroom, expandability etc. Current mirrors are mainly used for biasing, for transferring current from one part of the circuit to another or as load for amplifier stages. This paper presents the theoretical...
In this paper a novel high output impedance, low input impedance, wide bandwidth, very simple mirror/source structure with input and output voltage requirements less than that of a simple current mirror is presented. It can be also used as variable negative impedance converter (variable-NIC) by modifying amplifier transistors' aspect ratios. The circuit's principle of operation is discussed and compared...
This paper presents the new design of a CMOS current comparator for high speed and minimum size. This enables a very low response time to achieve high speed and less circuit complexity. In addition we have got less power consumption. A new current comparator exhibits high speed whilst maintaining low power consumption. Simulation results allow the design approach to be validated with performance comparison...
A low-power digitally-controlled variable gain low noise amplifier is implemented in a 40-GHz fT 0.25 ??m BiCMOS process. Wideband input matching independent of the variable gain, as well as high reverse isolation are achieved thanks to a partial feedback technique. The variable gain is based on a resistor-chain gain-control technique, leading to fine gain steps and constant output impedance. It covers...
This paper describes a CMOS LNA utilizing a folded cascade architecture for GPS front-end receiver in a TSMC 0.18-μm process. The major problem in the LNAs with folded cascade architecture is low reversing isolation. In this paper this parameter is improved by adding a transistor. The power gain and the minimal noise figure (NF) are two important factors for the circuits. Besides those factors, good...
High level integration for system on chip (SOC) applications motivates the development of broadband power amplifiers (PAs) in low cost CMOS technology to reduce size and power consumption of any wireless system. However, integration of one of the key components in a transmitter-the PA still remains a challenge. In this paper, a single stage broadband class-E PA based on lumped element load transformation...
Biasing digital CMOS circuits with rapidly changing supply current requires fast load regulation. Integrating the regulator with no external components on the same chip with the load circuit is attractive for applications with stringent volume and weight requirements. The purpose of this paper is the analysis, design and comparison of three structures of high-speed linear regulators implemented in...
As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by vertically stacking (i.e. cascoding) transistors becomes less useful in nano-scale CMOS processes...
In this work a design of a 2.4 GHz current reuse low noise amplifier (LNA) in a standard 0.35 mum SiGe technology is presented. In order to achieve good input matching for narrow bandwidth the inductive source degeneration LNA topology is used. Low power consumption with higher gain is obtained using current reuse configuration. In order to provide good isolation and stability cascode amplifier, as...
A high performance CMOS current differencing buffered amplifier (CDBA) is presented in this paper. The proposed circuit operates with the power supplies of plusmn0.75 V and consumes low power. HSPICE simulations show that the proposed CDBA provides better performance in nearly all parameters than the previous ones. As an application example, a second-order notch filter is chosen from the literature...
With the advent of miniaturised sensors for various engineering and medical applications there is an increased demand of low-power, low-voltage analog building blocks like opamps and OTAs. Degradation of certain amplifier characteristics with supply voltage is a major concern for low-voltage design and often poses contradictory requirement. CMRR (common mode rejection ratio), one such feature, is...
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