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An envelope modulator with hybrid topology for a high linearity and efficiency polar transmitter is described in this paper. The hybrid configuration exhibits a high speed and high efficiency combination by a linear amplifier and a switching amplifier, respectively, thereby improving the power added efficiency (PAE) of the polar transmitter. Moreover, to achieve wideband requirement, an operational...
We report the results of destructive and nondestructive heavy ion single-event effects (SEE) testing of the Intersil ISL71840SEH hardened 16-channel analog multiplexer, prefaced by a brief discussion of its functionality, electrical specifications and fabrication process.
The paper presents a new channel allocation method for higher Embedded Deterministic Test (EDT) compression in SoC designs comprising isolated cores. It employs a test data reduction technique, which allows cores to interface with ATE through an optimized number of channels. This feature is subsequently used by a new test scheduling and test access mechanisms devised for both the input and output...
In our previous work, a SDH Synchronous Links Organization Testing, Optimizing and Evaluating (SDH-SLOTOE) platform focusing on power communication networks has been founded supported by China Electric Power Research Institute (CEPRI). In this paper, SDH-SLOTOE is expanded to a PTN-SLOTOE platform. The Ethernet Synchronization Messaging Channel (ESMC) defined in ITU-T G.8264 is supported, and multi-standby...
Reversible logic is attracting the researchers attention for fault susceptible nanotechnologies including molecular QCA. In this paper, we propose concurrently testable FPGA design for molecular QCA using conservative reversible Fredkin gate. Fredkin gate is conservative reversible in nature, in which there would be an equal number of 1s in the outputs as there would be on the inputs, in addition...
According to the standard IEC 61508 fault insertion testing is required for the verification of fail-safe systems. Usually these systems are realized with microcontrollers. Fail-safe systems based on a novel CPLD-based architecture require a different method to perform fault insertion testing than microcontroller-based systems. This paper describes a method to accomplish fault insertion testing of...
Integrator leakage is a dominant factor in the SNR (signal-to-noise ratio) loss of DeltaSigma modulators. In this paper, we propose a design-for-test (DfT) technique to diagnose the integrator leakage of the single-bit first-order DeltaSigma modulator. The proposed technique is a low-cost solution; it only adds two multiplexers to the modulator, utilizes a single DC voltage as the test stimulus, and...
Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous...
A novel scheme for reducing the test application time in accumulator-based test-pattern generation is presented. The proposed scheme exhibits extremely low demand for hardware. It is based on a decoder whose inputs are driven by a very slow external tester. Experimental results on ISCAS benchmarks substantiate a test-time reduction of 75%-95% when compared to previously published test-set embedding...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
Many space systems require the multiplexing of high voltage analog signals around the spacecraft to drive actuators and motors for telemetry control. While considerable resources have supported the radiation hardening of digital electronics, very little has been focused on this critical high voltage analog requirement. To address this issue, Northrop Grumman has developed a radiation hardened high...
The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here a 12 bit 30 MHz analog to digital converter using a pipelined architecture. It is composed by ten 1.5 bit sub-ADC with a final 2 bit flash...
This paper describes a methodology for building a reliable internet core router that considers the vulnerability of its electronic components to single event upset (SEU). It begins with a set of meaningful system level metrics that can be related to product reliability requirements. A specification is then defined that can be effectively used during the system architecture, silicon and software design...
An on-line test methodology for MOSFET-C filters is presented, based on comparing the outputs from the different biquads in a filter to the output of a programmable biquad. The implementation of this biquad as well as that of a comparison circuit is discussed, and a design example is given.
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