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This paper presents the study, design and simulation of a laboratory module related to filters. With this laboratory platform it was accomplish a comparative study between current feedback (CFA) and voltage feedback (VFA). Because the laboratory platform has an educational role, it was presented some practical aspects of active filters measurement and also the differences between the measured values...
In this paper a design of two-stage CMOS operational amplifier for sigma-delta ADC is presented, which operates at ±1.8 V power supply using 180 nm technology. This two-stage CMOS OP-AMP has been designed to indicate a unity gain frequency of 18.2MHz and indicates a gain of 71.27 dB. The design and simulation part has been done on Cadence Custom IC CAD. The simulated results are encouraging and has...
A current-mode four-phase quadrature oscillator using 2 current controlled current conveyor transconductance amplifiers (CCCCTAs) and 2 grounded capacitors is presented. The proposed oscillator can provide 4 sinusoidal output currents with 90° phase difference. The oscillation condition and oscillation frequency can be electronically/independently controlled by adjusting the bias current of the CCCCTA...
In this paper, the critical impact of leakage current dispersion for a circuit with series connected electrolytic capacitors and a simple technique to improve are presented. The circuit is designed using four electrolytic capacitors in series connection to divide the dc bus voltage. For the ease of analysis an application of 36 volts with four equal 9 volts across capacitors is considered. Here, the...
A simple digital background-calibration technique is proposed for a pipelined analog-to-digital converter (ADC). Both gain error and DAC error are measured and calibrated by injecting two uncorrelated pseudo-random sequences into the MDAC. With this method, not only small capacitors might be used, leading to small chip size, but also the traditional current starving high gain op-amps of pipelined...
A 14bit MDAC with 120MS/s conversion rate, in 0.35um CMOS technology is presented. The MDAC consumes a power of 36mW from a 3.3v power supply and its settling time is 7ns. It utilizes a new high speed, high gain Op Amp, with 102dB gain, and 1.2GHz bandwidth. The phase margin of Op Amp is 51° and its settling time is 5ns for feedback gain of 8. The Op Amp has a good linearity of -60dB.
Mathematical equations are possible to simulate with various electronic circuits. Inductors and capacitors intrinsically are capable of integrating and differentiating, and active components alone can realize such algebraic operations as addition and multiplication. In this work, linear differential equations are shown to be implemented with three active components, namely operational amplifiers(Opamp),...
This paper presents a low-voltage low-power pipelined ADC with 1V supply voltage in a 90nm CMOS process. A new architecture is proposed to reduce the power consumption in high-speed pipelined analog-to-digital converters (ADCs). The presented architecture utilizes a combination of two current power-reduction techniques, double sampling and amplifier sharing. To decrease the power dissipation more...
A new electronically tunable single-element-controlled current-mode quadrature oscillator circuit using current differencing transconductance amplifiers (CDTAs) is presented. The proposed oscillator is consisted of two CDTAs, two grounded capacitors and one grounded resistor, which is beneficial to monolithic integrated circuit implementation. The oscillation condition and oscillation frequency of...
Operational amplifiers used in switch-capacitance applications must have high speed, high accuracy and low power consumption. In this paper a design method for a two-stage hybrid-cascade compensation operational amplifier based on settling behavior in closed-loop applications is proposed. This methodology, which optimizes the relationship between settling-time and bandwidth of an amplifier, has been...
This paper presents a high performance readout circuit for Infrared detector. The circuit is composed of capacitor trans-impedance amplifier (CTIA) and correlation double sampling (CDS) circuit. The CTIA structure is used to convert the photo-current into voltage, and could obviously improve the readout accuracy of weak current signal. And the CDS structure is used to reduce the fixed pattern noise...
This paper describes a digital calibration scheme for pipelined analog-to-digital converters (ADCs). The proposed method corrects the nonlinearity caused by finite gain and bandwidth of interstage operational amplifiers as well as the capacitors mismatch in multiplying digital-to-analog converters. The proposed calibration technique takes the advantages of both foreground and background calibration...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
This paper demonstrates a 0.8-V, 9-bit, 20-MS/s pipelined ADC with only 0.58 pJ-Volts/step. A novel circuit architecture which merges opamp-sharing with loading-free structure is proposed. Such mechanism effectively reduces the number of opamps as well as the capacitive loading. In addition, an inverse-flip-around sample-and-hold with unity-feedback factor is employed which further reduces the power...
An on-line tuning system based on the master-slave technique is proposed in this paper. The system is realized by employing only operational transconductance amplifiers (OTAs) for the realization of all stages. As a result, attractive offered benefits are the suitability of implementation of the resulted configurations in both integrated and discrete- component forms. In addition, an advantage of...
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