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Four-level hybrid-clamped (4L-HC) inverter is a newly proposed topology which is suitable for high-performance medium-voltage drives. This paper proposes a multi-objective optimization strategy for this 4L-HC inverter. The central DC-link capacitor and flying capacitor voltages are regulated by a modified phase-shifted PWM. The upper and lower capacitor voltages are balanced by zero-sequence voltage...
Focused on the current problems which exist in nine-area control strategy, such as frequent operation of control equipment and low qualified rate of voltage, the theory of nine-area method is deeply analyzed, and a new optimal setting method of reactive power interval in nine-area figure is proposed. A math model of evaluation function based on one-day energy loss of network, one-day adjusting times...
This paper presents a few design considerations in implementing building block-based Computer Aided Design (CAD) for analog switched circuits. The considered synthesis include four independent levels: 1) system level, 2) building block level, 3) circuit simulation level, and 4) layout generation, which multistage can separate a larger size circuit into a few major basic building blocks. The aim of...
This paper presents a new time-domain design procedure for three-stage amplifiers with reversed nested Miller compensation (RNMC). By utilizing this method, the values of the compensation capacitors are properly selected to achieve the best settling time. To demonstrate the effectiveness of the proposed method, a three-stage amplifier is designed and simulated in a 1V, 90nm CMOS technology. Simulation...
This paper deals with an optimization approach of a three-phases inverter associated to a bus capacitor filter and a heatsink. This approach considers multi-technology components and a power semiconductors generic modelling. The optimized choice is performed with a Genetic Algorithm (GA) with the help of components databases for the semiconductors, capacitors and heatsinks. The aim is to minimize...
Capacitor placement/setting is one of the main means for loss reduction and voltage profile improvement in distribution systems. If capacitor placement is meant, the objective function will be the cost of energy losses besides the capacitors costs in a specified period of time. Here, reconfiguration can be used as a strategy to reform the base configuration of the distribution network in order to...
In this paper, a new method is proposed for network loss and voltage deviation minimization in distribution networks. The proposed method makes use of multi-objective meta-heuristics (MOMH) that evaluates a set of the Pareto solutions systematically. The power networks become more deregulated and competitive due to the power liberalization. Hence, the cost minimization has been recognized as one of...
Capacitor placement/setting is one of the main means for loss reduction and voltage profile improvement in distribution systems. If capacitor placement is meant, the objective function will be the cost of energy losses besides the capacitors costs in a specified period of time. Here, reconfiguration can be used as a strategy to reform the base configuration of the distribution network in order to...
The lumped element model of CRLH - TL has been extracted using circuit modeling. Good agreement between the lumped element and EM simulations has been shown. An optimization based on the lumped element model was done in two steps: first optimization of the internal structure and second by optimization of the input and output interdigital capacitors. The final fabrication measurement test results show...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here a 12 bit 30 MHz analog to digital converter using a pipelined architecture. It is composed by ten 1.5 bit sub-ADC with a final 2 bit flash...
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