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In this article we propose the implementation of different RNS moduli sets on FPGA. We also reviewed methods for calculation of remainder of division by modules of special form. In addition, the application of logical sharing schemes with effective distributing of FPGA resources is presented in the paper. We modified the algorithm of residue calculation by using distributed arithmetic's methods and...
Super Resolution (SR) is an interesting topic in image and video research. Among SR Super Resolution Image Reconstruction (SRR) is one of the most common SR technologies. Originally SRR was proposed for still images. Recently SRR has been applied to video. However, there are important differences between still images and video that must be addressed when working with SRR. The basic hypothesis of SRR...
Floating point number can co-occurrently develop a prominent range of numbers and a high level of precision. Multiplication of floating point numbers found extensive use in wider range of technological and commercial calculations. It is needed to implement faster multipliers involving limited area and consuming reduced power. An IEEE-754 format established multiplier applying Vedic Urdhva — Tiryagbhyam...
The paper presents the design of a MAC unit that is based on the Vedic Square and its application, for the processing of equations that solely contain square terms. The use of Vedic Square as a replacement of the multiplier helps in reduction of area. In this paper, the Vedic Square is compared to the Vedic multiplier; both are based on the UrdhvaTiryagbhya sutra of Vedic mathematics. Duplex property...
The Discrete Cosine Transform (DCT) is the most widely used transform for image compression. The DCT approximation or the Binary Discrete Transform (BinDCT) [1] has shown to be a promising alternative to the DCT for its implementation simplicity, close performance and compatibility to the DCT. In this paper, we aim to present efficient VLSI architectures with a low BinDCT complexity implementation...
In recent years, reversible computation has received much attention in the field of low power circuit design. In this paper, an irreversible IG-A gate is presented. The gate is further used to design irreversible full adder/subtractor (IAS). Furthermore, IAS block is utilized to construct n-bit adder and subtractor. Proposed IAS design is analyzed and compared against the existing reversible methods...
CORDIC plural-multiplier is the key module to affecting the speed and accuracy of FFT processor. Considering these demands, the problem of CORDIC algorithm is discussed in detail and the according optimization methods are given in this paper. Then, the hardware pipelining structure of the CORDIC multiplier is put forward. Comparison results about RTL simulation results with MATLAB calculation indicate...
The hardware implementation of a high speed floating point multiplier with pipeline architecture based on FPGA is presented in the paper. In the design of the floating point multiplier, the utilization of a new radix-4 booth's encoding algorithm, the improved 4:2 compression structure and summation circuit is made to implement the compression of the partial products, and the sum and carry vectors...
The occurrence of errors are inevitable in modern VLSI technology and to overcome all possible errors is an expensive task. It not only consumes a lot of power but degrades the speed performance. By adopting an emerging concept in VLSI design and test-error-tolerance (ET), we managed to develop a novel error-tolerant adder which we named the Type II (ETAII). The circuit to some extent is able to ease...
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