The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A project-oriented course for advanced undergraduate and graduate students is described for simulating multiple processor cores. Simics, a free simulator for academia, was utilized to enable students to explore computer architecture, operating systems, and hardware/software cosimulation. Motivation for including this course in the curriculum is provided along with a detailed syllabus and an assessment...
rSesame is a generic modeling and simulation framework which can explore and evaluate reconfigurable systems at the early design stages. The framework can be used to explore different HW/SW partitionings, task mappings and scheduling strategies at both design time and runtime. The framework strives for a high degree of flexibility, ease of use, fast performance and applicability. In this paper, we...
This tutorial describes the design flows, that is, the design steps and software tools required for designing modern systems-on-chip, focusing on the front end part. A simple flow starting with abstract design description in an HDL and going through transformations leading to physical design, is no longer adequate for the complex systems of today. A high end MPSoC (multiprocessor system on chip) today...
PTL (projection temporal logic) is a kind of temporal logic which can handle both sequential and parallel computation. In this paper, we proposed a formal approach of specification and verification of SOC using PTL. With this approach, PTL is used in high level design and hardware/software co-design for the formal specification and verification of a SOC system or its hardware/software parts. A simple...
Larger last level caches are being considered for bridging the performance gap between the processors and the memory subsystem. It requires much longer simulation time to exercise the whole cache and get accurate evaluation results. In this paper, we motivate the need for a trace-driven hardware/software co-simulation approach to solve this problem. We describe the components of the hardware/software...
The hArtes -holistic approach to reconfigurable real time embedded systems- design flow addresses the development of an holistic tool-chain for reconfigurable heterogeneous platforms. The entire tool-chain consists of three phases: algorithm exploration and translation, design space exploration and system synthesis. This paper evaluates the tools in the design space exploration phase and the system...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.