The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Designers of complex SoCs have to face the issue of tuning their design to achieve low power consumption without compromising performance. A set of complementary techniques at hardware level are able to reduce power consumption but most of these techniques impact system performance and behavior. At register transfer level, low power design flows are available. Unfortunately, equivalent design flows...
This paper presents a low-power 11-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a self-dithering technique. The LSBs is employed as a dither to improve the resolution. Compared to converters that use the conventional dithering architecture, simulation results show that the proposed self-dithering technique improve the DNL performance with simplified...
This manuscript provides a novel method to improve occupied area, speed and power consumption of Infinite Impulse Response (IIR) decimation filter. The filter is design using proposed Merged Delay Transformed (MDT). First, mathematical calculation is performed and then applied effectively to first- and second-order IIR filters. The performance of the proposed design is compared with the exiting polyphase...
In this paper, a 6-bit 320-MS/s successive approximation register analog-to-digital converter (SAR ADC) is presented. The 2-bit/cycle technique and tri-level based charge redistribution technique are utilized to achieve high conversion rate and reduce the hardware cost. The proposed ADC is designed and implemented in a 65-nm CMOS process. Simulation results show that it accomplishes 48.52-dB SFDR,...
This paper presents a novel structure to implement the rational-powered membership functions (RPMF), that are the extended forms of triangular/trapezoidal membership functions and those functions which are generated by applying linguistic hedges. Proposed method is based on the approximation of the function (xa) by the functions square and square/rooter which are simply implemented in current mode...
In this paper, based on genetic algorithm (GA) an optimization approach is proposed to the arrangement of memory content in group distributed arithmetic (GDA) architecture with low power consumption. According to the information of data such as a kind of image sequence, we take one in the sequence to find an arrangement of memory content to have the near optimal transition activity on the data bus...
The occurrence of errors are inevitable in modern VLSI technology and to overcome all possible errors is an expensive task. It not only consumes a lot of power but degrades the speed performance. By adopting an emerging concept in VLSI design and test-error-tolerance (ET), we managed to develop a novel error-tolerant adder which we named the Type II (ETAII). The circuit to some extent is able to ease...
Power estimation and verification have become important aspects of System-on-Chip (SoC) design flows. However, rapid and effective power modeling and estimation technologies for complex SoC designs are not widely available. As a result, many SoC design teams focus the bulk of their efforts on using detailed low-level models to verify power consumption. While such models can accurately estimate power...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.