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How the virtualization can be used for research and development purpose across the corporate and enterprise by integrating it with other technologies? I would like to cover the integration of the virtual, real and simulated networks for research and development purpose of geographically spread organizations with diverse divisions. This will address the development of complex systems eliminating the...
Simulation of new multi- and many-core systems is becoming an increasingly large bottleneck in the design process. This paper presents the ACME design automation tool flow that facilitates the hardware emulation of newly proposed large multi-core interconnection networks on FPGAs to mitigate the slowdowns of single threaded event driven simulation. The tool is aimed at computer and network architects...
rSesame is a generic modeling and simulation framework which can explore and evaluate reconfigurable systems at the early design stages. The framework can be used to explore different HW/SW partitionings, task mappings and scheduling strategies at both design time and runtime. The framework strives for a high degree of flexibility, ease of use, fast performance and applicability. In this paper, we...
Distributed shared memory (DSM) machines provide the shared memory paradigm and achieve high performance by the caching of shared data. However, they suffer from cache miss and remote access latency with coarse-grain patterns. In this paper we suggest the combination of bulk transfer and prefetching as a new latency hiding technique in DSM machines. The purpose of bulk transfer is to replicate remote...
The locality of data reference affects system performance significantly in distributed shared memory systems. One method of improving the performance is to use data allocation methods reflecting the locality of data references. This paper proposes a cache coherence scheme by utilizing the near processor locality, and evaluates its performance. The proposed scheme reduces memory overhead by using a...
As microprocessors continue to evolve, many optimizations reach a point of diminishing returns. We introduce HLS, a hybrid processor simulator which uses statistical models and symbolic execution to evaluate design alternatives. This simulation methodology allows for quick and accurate contour maps to be generated of the performance space spanned by design parameters. We validate the accuracy of HLS...
The cost, complexity, and inflexibility of hardware-based directory protocols motivate us to study the performance implications of protocols that emulate directory management using software handlers executed on the compute processors. An important performance limitation of such software-only protocols is that software latency associated with directory management ends up on the critical memory access...
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