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Quantum cellular automaton (QCA) is an efficient and emerging nanotechnology to create quantum computing devices. It is polarization based digital logic architecture. QCA cell is the basic unit to build logic gates and devices in quantum domain. This paper proposes an effective design of logic gates and arithmetic circuit using QCA. Here the gates and circuits are designed using minimum number of...
The single message ferry routing scheme works well in the small scale clustered DTNs (Delay/Disruption Tolerant Networks). However, as the increasing of the network scale, this scheme will lead to high delay. To solve this problem, a hierachical multiple ferries routing scheme (HMFRS) was proposed in this paper. In this scheme, a message ferry and a ferry access point are deployed in each DTN cluster,...
This paper proves feasibility of a fully distributed automation design of Baggage Handling Systems automation. The proposed design methodology leverages IEC 61499 Function Blocks as a supporting architecture. Each physical element of the BHS, such as a conveyor is represented by a Function Block that encapsulates functionality into a single re-usable module. The proposed solution demonstrates such...
In this paper we present a remote utility metering system based on ZigBee used to collect data from residential electricity, gas and water meters. In order to reduce the use of network resources and to evaluate the sensor network performance, a simulation study was carried out with two types of data related to electronic and non electronic metering devices. The study was conducted using a simulator...
We introduce a method of partitioning for massively-parallel hardware accelerated functional verification. Our approach augments classical hypergraph partitioning to model temporal dependencies that maximize parallelization within the instruction memories of the machine. Simulation depth is further reduced by optimizing path criticality and cut directionality. Our techniques are demonstrated on an...
PCE is an emerging technology to aggregate path computation tasks in some certain elements. The location of these elements may influence network performance. In this paper, an ILP model for PCEs location problem is formulated and a heuristic algorithm is proposed. Simulations are conducted to evaluate the effectiveness of the algorithm presented.
In this paper a MAC protocol with dynamic priority adjustment for light trail networks is presented. A weight mode which is composed of real-time factor and node activity ratio is used as a bid by each node to compute the priority. Simulation results show that DPA MAC reduced the burst loss rate and improved activity percentile when compared with FP MAC.
In this paper we propose a router-sharing architecture for 3D NoC which outperforms existing 3D NoC designs under thermal impacts. According to thermal simulations, in conventional designs, the routers on the top layers far from the heat sink have to be disabled frequently to avoid thermal emergency. Therefore, the proposed architecture removes all routers on the top layers and uses only buses to...
This paper presents the realization of the 1GHz Negative Logarithmic Function (NLF) based on the 0.35um AMS technology. Firstly, it shows some interesting advance beyond Mitchell's approach with hardware implementation of a sequential architecture minimized in terms of gates and thus optimized for power and area sensitive application. Secondly, it introduces the realization of the NLF using combinational...
Levy Flight is a special kind of random walk model. According to the past studies, the foraging patterns of animals follow a Levy flight distribution. Delay and disruption Tolerant Network(DTN) is a special network adapted to a special restricted network communication environment. In this paper, we proposed a new DTN model: BirdNet, which is based on fast-moving sensor nodes installed on the birds...
rSesame is a generic modeling and simulation framework which can explore and evaluate reconfigurable systems at the early design stages. The framework can be used to explore different HW/SW partitionings, task mappings and scheduling strategies at both design time and runtime. The framework strives for a high degree of flexibility, ease of use, fast performance and applicability. In this paper, we...
We consider a relay-assisted wireless communication system where relays are given the capability of scheduling function. We evaluate and compare the performances of voice over internet protocol (VoIP) in orthogonal frequency division multiple access (OFDMA) systems where two different scheduling capabilities of relays are employed in each system. In the system with relays that have the scheduling...
In order to reduce handover delay caused by handover failure, radio resource is reserved for handover users not only at target cell, but also at prepared cells. This has been agreed in 3GPP LTE. However, these reserved resources cannot be assigned for other users until the finishing of the handover, which results in inefficiency of radio resource utilization. This paper presents a new resource reservation...
This paper designs a PCE-based architecture of routing, and proposes two distributed signaling schemes in PCE-based wavelength switching optical network (WSON). Simulation results based on the topology of Chinese core network are given and analyzed.
For the different communications of specific NOC (network on chip) applications, this paper proposes a customized arbitral priority NOC router. This router uses the arbitral mechanism based on lottery algorithm instead of the RR (round robin) algorithm, which is widely used in the arbiter of current NOC routers. The arbitral priority of lottery router can be customized by users according to the communication...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
With the event of nanoscale technologies, new physical phenomena and technological limitations are increasing the process variability and its impact on circuit yield and performances. Like combinatory cells, the sequential cells also suffer of variations, impacting their timing characteristics. Regarding the timing behaviors, setup and hold time violation probabilities are increasing. This article...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
This paper compares readout powers and operating frequencies among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM. The conventional 8T SRAM has the least transistor count, and is the most area efficient. However, the readout power becomes large and the cycle time increases due to peripheral circuits. The 10T single-end SRAM is our proposed SRAM, in which a dedicated inverter...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
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