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Compact diode models normally available in commercial simulators like Spectre or HSPICE do not scale the series resistance with P-N distance. The standard diode models scale with drawn area, assuming the current is vertical. However the diodes used for ESD protection in CMOS are operating as lateral diodes, so the resistance should scale with width, not area. This is a serious problem for circuit...
Unexpected functional failures were found in the core of an IC, processed in a 65 nm technology with 1.8 nm gate oxide after MM testing, although a comprehensive rail-based protection scheme was applied. Failure analysis was performed including Obirch, backside de-processing, and SEM analysis to locate the failure in the gate oxide of several core NMOS transistors. Careful TLP measurements on NMOSTs...
A non-self protection ESD scheme using grounded-gate, gate non-silicided (GG-GNS) drain/source silicide blocked (SBLK) ESD NFET offered in 45 nm SOI CMOS technology is presented based on a comprehensive study using the high current pulse characteristics. The results show that with a minimum SBLK width over drain/source, GG-GNS NFET can handle ~3.4 mA/mum current.
The ESD Associationpsilas Workgroup 5.5 subcommittee is conducting a round robin study to determine the repeatability and reproducibility of measurements made the current VF-TLP Standard Practice. This study involves seven test sites with eleven different test structures evaluated at each site. This paper summarizes these findings to date.
For the first time, damage thresholds for TMR and GMR read sensors were measured using pulses with widths ranging from 40 ps to 2.3 ns. The ultra-fast pulses were generated using a novel Ultra-Fast Transmission Line Pulsing (UFTLP) system. The damage voltage level for the TMR and GMR heads was about 0.6 V using 2.3 ns-wide pulses, and increased to about 2.0 V using 40 ps-wide pulses. However, the...
Carbon based static dissipative plastics have been widely used in electronic industries for electrostatic discharge protection and prevention. Carbon nanotubes plastic, a new material candidate, holds many superior properties which benefit the electronics industry. The electrical performance advantages of carbon nanotubes plastic, such as electrical uniformity, part-to-part consistency and inter-part...
A simple, area and power-loss efficient, portable and robust ESD protection method for DC/DC converters is presented. The method is based on MOS transistors operating in normal mode, replacing the snapback based design methods. Measurement results of a prototype fabricated on silicon showed good agreement with simulation and are reported.
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