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In this decade, the Moore's law does not fit the trend of technological improvement any more. In order to keep the increasing rate of device density and I/O numbers, the size of devices shrink rapidly. In this kind of condition, the stack of integrated circuit (IC), which is also called three-dimensional integrated circuits (3-D ICs), is a preferable solution of the next-generation products. There...
Traditional thermal loading test neglects the influence of power applied to PoP. To address this challenge, board level reliability of PoP subjected coupled thermal and power loadings were investigated in this study. In order to provide the coupled thermal and power loadings, high temperature storage (HTS) and constant current source were chosen for the accelerated test. Five test conditions (0A,...
Electronics is already established as an integral part of modern vehicles. In order to enforce recycling and recovery of vehicles, the End-of-Life Vehicles legislation was developed in the EU. This directive includes bans for certain substances (especially lead). Compared to the lead-free soldering the assembly of electronic devices using electrically conductive adhesives (ECAs) has a number of technological...
In this study, the reliabilities of low Ag SAC alloys doped with Mn or Ce (SACM or SACC) were evaluated under JEDEC drop, dynamic bending, thermal cycling, and cyclic bending test conditions against eutectic SnPb, SAC105, and SAC305 alloys. The Mn or Ce doped low cost SAC105 alloys achieved a higher drop test and dynamic bending test reliability than SAC105 and SAC305, and exceeded SnPb for some test...
Board level solder joint reliability was evaluated using a 4-point monotonic bending test on different BGA package assemblies, including a 51 ?? 51 mm 2400 CBGA and a 40 ?? 40 mm 1517 PBGA. The edgebond epoxy was applied between the package samples and solder-attached printed wiring boards (PWBs). During the bending test, the PWB strain, bending force and daisy-chain resistance were monitored in real...
The Package on Package (PoP) component is getting attentions in mobile communication electronics industry to meet the miniaturization requirements. The 3D IC packaging technology is employed to achieve higher integrations for multiple functions. This also concurrently reduces the size of PCB during second level of interconnection. Currently, there are two major approaches for system manufactures....
This study concerns the failure mechanism of a lead-free SAC305 solder joint under the isothermal bending fatigue condition. For this, series of bending fatigue tests are carried out with the variations of bending displacement and frequency, and FEM analysis is conducted to examine the relationship between mechanical behavior of a solder joint and fatigue life cycle. The results of this investigation...
Leading indicators of failure have been developed based on high-frequency characteristics, and system-transfer function derived from resistance spectroscopy measurements during shock and vibration. The technique is intended for condition monitoring in high reliability applications where the knowledge of impending failure is critical and the risks in terms of loss-of-functionality are too high to bear...
Two commonly used Pb-free solders, SnAg and SnCu, are studied for electromigration (EM) reliability. Two major EM failure mechanisms are identified in Sn-based Pb-free solders, which is mainly due to the differences in microstructures and Sn-grain orientation. In general, the EM damage in SnCu solder is driven by the fast interstitial diffusion of Ni and Cu away from solder/UBM interface and leads...
Flip chip technology is now being introduced in PoP(Package on Package) packages for the digital consumer electronics such as digital still cameras and mobile phones. PoP reduces the component height and improves the electrical performance. A MPS-C2(Metal Post Solder Chip Connection) method was developed for ultrafine pitch flip chip interconnections in mobile applications. A bare die with Sn/Ag-solder-capped...
This paper focused on design, assembly and reliability assessments of 21 ?? 21 mm2 Cu/Low-K Flip Chip (65 nm technology) with 150 ??m bump pitch. Metal redistribution layer (RDL) and polymer encapsulated dicing lane (PEDL) were applied to the chip wafer to reduce the shear stress on the Cu/low-K layers and also the strain on the solder bumps. The first level interconnects evaluated were Pb-free (97...
The reliability of BGA assembly packages were evaluated by rapid fatigue life test. Three-point bend fatigue life test method has been developed for Sn-Ag-Cu 305 and rare-earth addition Sn-Ag-Cu-Ce solder joints. In this study, BGA assembly with Ni/Au surface finish was tested under cyclic bending load at room temperature. The bending fatigue life of Sn-Ag-Cu 305 solder joint was compared with rare-earth...
Environmental regulations around the world have been targeted to eliminate the usage of leaded solders in electronic assemblies. Sn-Zn based alloys are considered to be a very promising candidate for its substantially same melting point as Sn-Pb solder. Fujitsu Limited has developed several lead-free solders with low melting point such as Sn-7Zn-30 ppmAl and Sn-9Zn-30ppmAl. Those solders have already...
This study demonstrates the value of RF impedance measurements as an early indicator of physical degradation of solder joints compared to DC resistance measurements. Mechanical fatigue tests have been conducted with an impedance-controlled circuit board on which a surface mount component was soldered. Simultaneous measurements were performed of DC resistance and the time domain reflection coefficient,...
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