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In this paper, an efficient multi-mode CORDIC processing unit is implemented on a dynamically reconfigurable array. The array consists of 4×4 multi-functional Processing Elements (PEs). An efficient pipelined data-flow graph is proposed to implement to achieve a high data throughput and, in the same time, maximizing the resource utilization rate. The implementation results shows that, when compared...
In this paper, we discuss and evaluate about a grain size of the PE of a matrix operation specific architecture with fused multiply add (FMA) units, Rapid MatriX, on FPGAs. Recent FPGAs have many DSP blocks which are high-performance arithmetic units. Hereby, implementing functional units for matrix operation to array structure of the Rapid MatriX, we propose to use DSP blocks efficiently by increasing...
Intra prediction algorithm in the recently developed High Efficiency Video Coding (HEVC) standard has very high computational complexity. Therefore, in this paper, we propose novel techniques for reducing amount of computations performed by intra prediction algorithm in HEVC decoder, and therefore reducing energy consumption of intra prediction hardware in HEVC decoder. The proposed techniques significantly...
String matching is a ubiquitous problem that arises in a wide range of applications in computing, e.g., packet routing, intrusion detection, web querying, and genome analysis. Due to its importance, dozens of algorithms and several data structures have been developed over the years. A recent breakthrough in this field is the FM-index, a data structure that synergistically combines the Burrows-Wheeler...
The security of digital images attracts much attention recently. For images the transformation can be implemented at two levels, the first one consists of the pixel value permutation and the second one consists of position permutation. In this paper, we propose an encryption scheme for digital images with new pixel position permutation method based on Evolvable Hardware (EHW). In this work, we use...
In this paper, we describe an approach for detecting patterns in various size and angle using FPGA. In many approaches, features of a given pattern which are invariant to scaling and/or rotation are defined in advance, and those features are searched in a given image. These approaches make it possible to narrow down the candidate regions with less computational cost, but the sensitivity depends on...
RNA folding is a compute-intensive task that lies at the core of search applications in bioinformatics such as RNAfold and UNAFold. In this work, we analyze the Zuker RNA folding algorithm, which is challenging to accelerate because it is resource intensive and has a large number of variable-length dependencies. We use a technique of Lyngso to rewrite the recurrence in a form that makes polyhedral...
In this article we describe our effort to create, model, implement and simulate a quadrature linear digital modulator. It is to be used as a part of advanced radio transmission system. We describe the process of modeling the modulator in Matlab in both floating and fixed point arithmetic for later implementation in VHDL language for FPGA. We also describe the techniques we have used to implement the...
When targeting algorithms to FPGAs both the array to memory assignment and the selection of data reuse structures should be considered to maximise performance. In this work we present an integer linear programming formulation for the combined problem of array to memory assignment and data reuse selection. We include a number of cost functions to minimise during memory optimisation and show how these...
We propose an efficient multi-access memory architecture for image applications with multiple interested regions. Conflict-free parallel access of randomly aligned rectangular blocks of data in the interested regions is achieved. Only interested regions in the image are transmitted from main memory to a secondary multi-module memory structure proposed in our work, and overlapped data between different...
Many researchers have been interested in the processor-memory bottleneck problem. Quite a few image applications are only interested in one or more partial regions in the images. This paper proposes an efficient multi-access memory scheme for these image applications with multiple interested regions. A multi-module memory structure is presented between the main memory and the processing units, which...
To deal with the problem of maintaining variable data set in digital image processing, this paper brings forward a general hardware structure for linked-list. It is designed to accomplish the commonly used functions and some more complicated functions of the linked-list data structure. In order to fully utilize the limited memory resources in embedded hardware platform, we propose a memory recycle...
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