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With the increase of data rate, signal integrity (SI) becomes a bigger challenge for printed circuit board (PCB) designs. Power noise as well as signal loss, inter-symbol interference (ISI), crosstalk needs to be taken into account to ensure a good quality signal design. In this paper, a design case is shared where power noise greatly impacts SATA performance and leads to hard disk (HDD) disconnection...
Crosstalk noise is a critical issue in the deep submicron circuit design, since it causes functional failures in IC chips. This paper proposes an efficient approach to find the timing region of the circuit that timing failure occurs in an IC chip. The proposed method efficiently finds timing failure region by using CGOV metric without iterative simulations. In the experimental results, the proposed...
Designing high speed Double Data Rate (DDR) memory interface controller in low cost wire-bond packages is a difficult goal to achieve. The interface is limited at speed because of various factors such as Inter Symbol Interference (ISI), Power Delivery Network (PDN) noise, Cross talk etc. At high speeds like 1Gbps, Pattern dependent effects have a major role to play in DDR link budget analysis. Hence,...
As technology feature geometries shrink, failures caused by signal integrity issues have become prominent during test. To avoid the time consuming silicon inspection and reduce the engineering cost and effort for failure analysis, a fast and cost-effective diagnostic flow is proposed in this paper. The flow targets delay faults and can be used to (1) identify noise-related failures with a quiet pattern...
In DSM technology and beyond, the performance and correctness of the circuit cannot be assured without taking into consideration the multiple effects of interconnect parasitics. The inter wire parasitics i.e. mutual inductance and coupling capacitance are primary sources of crosstalk noise. In this paper, the optimization of coupling capacitance for delay and peak noise is carried out qualitatively...
Future interconnection subsystems for switches and routers must overcome physical limitations of current electronic backplanes in order to achieve aggregate bandwidth much greater than today. Driven by this consideration we study the scalability of switching architectures implementing backplanes based on optical interconnection technology. In particular, this paper deals with the issue of interconnecting...
This paper discusses the challenges in system level timing closure of a high speed DDR interface. The different aspects of the DDR controller, I/O buffer, package and board to be modeled for ensuring stable operation at the targeted speed are described.
This paper illustrates some design strategies for the design of mixed analog-digital integrated circuits in CMOS technology. In mixed-signal systems, crosstalk from switching logic gates can disturb the operation of analog circuitry. Therefore, it is necessary to take into account digital switching noise from early stages of design, by means of a suitable model. The analog designer should select the...
Through-strata-via (TSV) is regarded as a critical component in 3D integration that extends Moore's Law. This paper reports on TSV crosstalk performance under high speed operations using a 3D electromagnetic field solver and a SPICE simulator in both the frequency domain and time domain. Impacts of the rise time, the TSV pitch/height, the substrate resistivity and the guarding TSV termination on crosstalk...
This paper discusses the challenges in system level timing closure of a high speed DDR interface. The different aspects of the DDR controller, I/O buffer, package and board to be modeled for ensuring stable operation at the targeted speed are described.
In DSM technology, unintended interactions between signals propagating through interconnect turn out to be critical design concern. At technology nodes below 0.25μm, the performance and correctness of a design cannot be assured without considering noise effects. In integrated circuits, the main cause of signal integrity problems is crosstalk. This paper presents the effects of aggressor driver width...
Modeling the effect of coupling-noise on circuit delay is a key issue in static timing analysis and involves the victim-aggressor alignment problem. As delay-noise strongly depends on the skew between the victim-aggressor driver input transitions, it is not possible a priori identify the victim-driver input transition that results in the worst-case delay-noise. Several approaches have been proposed...
A 40 mW 0.059 mm2 analog video pre-processing is presented. Pseudo differential inputs and an AGC with two gain characteristics are implemented. These gain characteristics are realized by simply adding one resistor to the existing topology. Two single ended low noise input buffers are used in unity gain configuration to operate the AGC. The ADC is driven by a binary weighted 4th order Bessel filter...
Constant evolution in integrated circuit technology has led to an increase in digital chip switching speed. There is thus growing interest in inductance associated with signal lines. In this study, for a three coupled-line distributed system, it is demonstrated that crosstalk voltages observed at their termination result from output modal voltage combinations generated when a mode propagates under...
Commercial crosstalk analysis tools are widely used for timing verification of LSI, but they analyze the worst case of crosstalk effect in any theoretical cases, which is really pessimistic. Some works have been done to reduce the pessimism based on deterministic method like logical correlation or timing window correlation. In this paper, a novel and practical crosstalk analysis introducing probability...
The problem of calculating accurate impact of crosstalk on a circuit considering its inherent logic and timing properties is very complex. Although it has been widely studied, it still lacks an efficient solution. As a result, state-of-the-art crosstalk calculators use simplistic and overly pessimistic models resulting in the over-estimation of crosstalk effects. Such pessimism in crosstalk analysis...
Crosstalk noise becomes one of the critical issues gating design closure for nano-meter designs. Pessimism in noise analysis can lead to significant additional time spent addressing false violations. Taking logic correlation into consideration, noise analysis can reduce pessimism significantly by eliminating false noise signals [1]-[3][5]-[7][10]-[13]. Eliminating the aggressors from the aggressor...
In this paper, we consider the problem of selecting a set of aggressor nets that maximize crosstalk induced noise or delay pushout on a coupled victim net, under given logical constraints. We formulate the problem mathematically, and propose efficient Lagrangian Relaxation and network flow based approaches that guarantee an optimal solution. We also formulate and solve this problem while considering...
Due to advanced process technologies the decreasing distance between wires has led to significant bus interferences that introduce crosstalk delay and noise. We first propose two encoding schemes, namely DUCE and GASIE, that can reduce crosstalk delay and noise on the bus lines. The DUCE scheme is a temporal encoding so it needs no additional bits to implement. It can be easily used in existing systems...
As technology scales, inductive crosstalk becomes prominent along with capacitive crosstalk, and it is creating a significant bottleneck in high-speed deep sub-micron and nanoscale integrated circuits. For inductive coupling, worst-case delay occurs when all the bus lines simultaneously switch in the same direction. This switching case is the best case switching pattern for capacitive-dominant on-chip...
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