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An edge switch is an operation on a network (graph) where two edges are selected randomly and one of their end vertices are swapped with each other. Usually, a sequence of these operations are performed to generate network perturbations having the same degree sequence of the original network. Edge switch operations have important applications in graph theory and network analysis, such as in generating...
Collective operations, such as allreduce, are widely treated as the critical limiting factors in achieving high performance in massively parallel applications. Conventional host-based implementations, which introduce a large amount of point-to-point communications, are less efficient in large-scale systems. To address this issue, we propose a design of switch chip to accelerate collective operations,...
Serial RapidIO is a high-performance, packet-switched that was developed to address the embedded industry's need in term of faster bus speeds, increased bandwidth and reliability. Serial RapidIO allows chip-to-chip and onboard communications. In this paper, we present experimental results on performances optimizations of the Serial RapidIO interconnect integrated in the new digital signal processor...
Saving energy is one of the principal challenges in wireless sensor networks. Dynamic voltage and frequency scaling (DVFS) is often used to reduce energy consumption in systems where sleep is not an option. We show that changing the CPU frequency introduces sudden changes in clock behavior, thereby affecting the time-keeping functionality. This anomalous phenomenon is observed in different sensor...
The multiprocessor system-on-chip (MPSoC) uses multiple CPUs along with other hardware subsystems to implement a system. So on-chip communication requirements of many systems are best served through the deployment of a regular chip-wide network. This paper presents the design of a crossbar for network router for such applications. Simulations illustrate how the performance and area of whole router...
One of the main challenges in the multi-core area is the communication and synchronization of the cores and the design of an efficient interconnection network that is scalable to multiple cores. In this paper we present an efficient implementation of a scalable system that is targeting multi-core systems. Each cluster node consists of 4 processors that support both explicit and implicit communication...
POOSL (Parallel Object-Oriented Specification Language) is a powerful general purpose system-level modeling language. In research on design space exploration of motion control systems, POOSL has been used to construct models for performance analysis. The considered motion control algorithms are characterized by periodic execution. They are executed by multiple processors, which are interconnected...
With the wide availability of chip multi-processing (CMP), software developers are now facing the task of effectively parallelizing their software code. Once they have identified the areas of parallelization, they will need to know the level of code granularity needed to ensure profitable execution. Furthermore, this problem multiplies itself with different hardware available. In this paper, we present...
In this paper, we focus on the problem of implementing a periodic concurrent system with timing constraints into multi-context dynamically reconfigurable processors (DRP). A concurrent system has multiple tasks that can be executed in parallel. Moreover, some tasks in a specific set of processes might be required to synchronize each other. We propose a method for assigning tasks into a multi-context...
This paper presents architecture for accelerating message switch and synchronization performed in a message passing library developed on Maestro3 cluster network. Maestro3 is a high-performance cluster network that has the optimized data link layer and the capability of dynamic offload. We propose the dedicated hardware for further improvement of communication performance. In this paper, detailed...
A real-time operating system (RTOS) is software which ensures that time critical events are processed as efficiently as possible. In this paper, an attempt has been taken to develop a real time operating system, named preemptive real time operating system (pRTOS), in which all of the important issues regarding to a real time application have been considered. In this pRTOS, strictly preemptive scheduling...
We describe a Data Acquisition and Analysis Platform (DAAP) based on the ATCA specification. The DAAP was designed for use in a multi-plane tomosynthesis X-ray imaging system but its architecture was generalized to support wide range of data acquisition, routing, and processing applications.
Next generation Navy platform designs are evolving towards generalized multipurpose infrastructures based on open standards and commercial products. These platforms will support a wide range of new and expanding applications in a more flexible and dynamic manner than in previous designs. These applications are increasingly being more finely partitioned and distributed over this generalized infrastructure...
The use of the controller area network communication protocol for H-bridge multilevel (HBML) inverters, and localized pulsewidth modulation generation and automated voltage regulation is proposed in this paper. It is shown that the performance and reliability of conventional distributed controllers for HBML inverters can be improved with less communication hardware requirements, when using the proposed...
It is becoming increasingly difficult to implement effective systems for preventing network attacks, due to the combination of (1) the rising sophistication of attacks requiring more complex analysis to detect, (2) the relentless growth in the volume of network traffic that we must analyze, and, critically, (3) the failure in recent years for uniprocessor performance to sustain the exponential gains...
Sublinear signal propagation delay in VLSI circuits carries a far greater penalty in wire area than is commonly realized. Therefore, the global complexity of VLSI circuits is more layout dependent than previously thought. This effect will be truly pronounced in the emerging wafer scale integration technology. We establish lower bounds on the trade-off between sublinear signalling speed and layout...
Fat-trees are a class of routing networks for hardwareefficient parallel computation. This paper presents a randomized algorithm for routing messages on a fat-tree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor λ = Ω(lg n lg...
The architecture of a multicomputer system with switchable main memory modules (SM3) is presented. This architecture supports the efficient execution of parallel algorithms for non-numeric processing by 1) allowing the sharing of switchable main memory modules between computers, 2) supporting network partitioning, and 3) employing global control lines to efficiently support inter-processor communication...
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