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After four successful JUnit tool competitions, we report on the achievements of a new Java Unit Testing Tool Competition. This 5th contest introduces statistical analyses in the benchmark infrastructure and has been validated with significance against the results of the previous 4th edition. Overall, the competition evaluates four automated JUnit testing tools taking as baseline human written test...
Refactoring restructures a program to improve itsreadability and maintainability, without changing its originalbehavior. One of the key steps in refactoring is the identification ofpotential refactoring opportunities. In this paper, we discuss therelevance of two popular refactorings "Replace Type Code withSubclass" and "Replace Type Code with State" in real world Javaapplications...
Large scale simulation performance is dependent on a number of components, however the task of investigation and optimization has long favored computational and communication elements above I/O. Manually extracting the pattern of I/O behavior from a parent application is a useful way of working to address performance issues on a per-application basis, but developing workflows with some degree of automation...
In order to compare and rank the worlds fastest computers, benchmarks evaluating their performance are required. A single execution of HPL is used for the most widely recognized ranking: the TOP500. Lately, two benchmarks, arguably more representative of typical modern workloads, have been proposed: HPCG and HPGMG. Currently, all three benchmarks use the highest observed performance from a single...
Virtual platforms provide benefits to developers in terms of a more rapid development cycle since development may begin before next-generation hardware is available. However, there is a distinct lack of graphics virtualization in industry-grade virtual platforms, leading to performance issues that may reduce the benefits virtual platforms otherwise have over execution on actual hardware. This paper...
Software systems are often developed and released without formal specifications. For those systems that are formally specified, developers have to continuously maintain and update the specifications or have them fall out of date. To deal with the absence of formal specifications, researchers have proposed techniques to infer the missing specifications of an implementation in a variety of forms, such...
While high performance computing (HPC) is flourishing these years, the lack of HPC applications is increasingly serious. Conventional binary translation focused on desktop applications and embedded software, which could not be scaled up to HPC. This paper proposed a novel static binary translator MPI-QEMU aiming at MPI programs, the most commonly used on HPC platforms. Firstly, the efficient dynamic...
Transactional Memory is a concurrent programming abstraction that overcomes several of the limitations found in traditional synchronization mechanisms. As it is a more recent abstraction, little is known about energy consumption of Software Transactional Memories (STM). In this context, this work presents an analysis and characterization of energy consumption and performance of four Transactional...
The demand for parallel I/O performance continues to grow. However, modelling and generating parallel I/O work-loads are challenging for several reasons including the large number of processes, I/O request dependencies and workload scalability. In this paper, we propose the PIONEER, a complete solution to Parallel I/O workload characterization and gEnERation. The core of PIONEER is a proposed generic...
Over the last decade, the looming power wall has spurred a flurry of interest in developing heterogeneous systems with hardware accelerators. The questions, then, are what and how accelerators should be designed, and what software support is required. Our accelerator design approach stems from the observation that many efficient and portable software implementations rely on high performance software...
Manycore systems are becoming more and more powerful with the integration of hundreds of cores on a single chip. However, writing parallel programs on these manycore systems has become a problem since the amount of available parallel tools and applications are limited. Although exploiting parallelism in software is possible, it requires different design decisions, significant programmer effort and...
Code reuse attacks (CRAs) are recent security exploits that allow attackers to execute arbitrary code on a compromised machine. CRAs, exemplified by return-oriented and jump-oriented programming approaches, reuse fragments of the library code, thus avoiding the need for explicit injection of attack code on the stack. Since the executed code is reused existing code, CRAs bypass current hardware and...
With the omnipresent usage of APIs in software development, it has become important to analyse how the routines and functionalities of APIs are actually used. This information is in particular useful for API developers, to make decisions about future updates of the API. However, also for developers of static analysis and verification tools this information is highly important, because it indicates...
Software Managed Multicore (SMM) architectures have been proposed as a solution for scaling the memory architecture. In an SMM architecture, there are no caches, and each core has only a local scratchpad memory. If all the code and data of the task to be executed on an SMM core cannot fit on the local memory, then data must be managed explicitly in the program through DMA instructions. While all code...
An instruction-words based software birthmark is proposed by applying the idea of document copy detection technology based on word frequency. The birthmark extraction algorithm consists of two steps. Firstly, an instruction-word library is established by taking statistic on instruction combinations of program samples, and then instruction-words are extracted according to the instruction-word library...
Code reuse attacks (CRAs) are recent security exploits that allow attackers to execute arbitrary code on a compromised machine. CRAs, exemplified by return-oriented and jump-oriented programming approaches, reuse fragments of the library code, thus avoiding the need for explicit injection of attack code on the stack. Since the executed code is reused existing code, CRAs bypass current hardware and...
Software transactional memory (STM) is a promising programming paradigm for shared memory multithreaded programs. In order for STMs to be adopted widely for performance critical software, understanding and improving the cache performance of applications running on STM becomes increasingly crucial, as the performance gap between processor and memory continues to grow. In this paper, we present the...
This paper will present the results of porting the Extended Kalman Filter (EKF) Simultaneous Localization and Mapping (SLAM) Natural Feature Tracking (NFT) algorithm using the Automatically Tunable Linear Algebra System (ATLAS) for use in Tilera's Tile64 or OPERA's Radiation-Hardened By Design (RHBD) Maestro chip. 12This implementation of EKF SLAM was previously analyzed for performance on a RAD750...
In order to increase our ability to use measurement to support software development practise we need to do more analysis of code. However, empirical studies of code are expensive and their results are difficult to compare. We describe the Qualitas Corpus, a large curated collection of open source Java systems. The corpus reduces the cost of performing large empirical studies of code and supports comparison...
This work concerns the application of CUDA-based software (Compute Unified Device Architecture), developed by NVIDIA for programmable Graphics Processing units (GPUs). CUDA code is written in 'C for CUDA', indicating the standard C programming language with NVIDIA extensions.Our goal was to find out, whether batched (multiple) one-dimensional Fast Fourier Transformation (1DFFT), often encountered...
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