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GRVI is an FPGA-efficient RISC-V RV32I soft processor. Phalanx is a parallel processor and accelerator array framework. Groups of processors and accelerators form shared memory clusters. Clusters are interconnected with each other and with extreme bandwidth I/O and memory devices by a Hoplite NOC with 300-bit links. An example Kintex UltraScale 040 system has 400 RISC-V cores, peak throughput of 100,000...
Security has become a very demanding parameter in today's world of speed communication. It plays an important role in the network and communication fields where cryptographic processes are involved. These processes involve hash function generation which is a one-way encryption code used for security of data. The main examples include digital signatures, MAC (message authentication codes) and in smart...
Targeting the rapid development, with reduced complexity, of power converters control techniques, a field-programmable gate array (FPGA) based platform is proposed. The aim of the platform is to provide an effective support to the developer in the error-prone process associated to a traditional FPGA design flow. This work also enables remote hardware reconfiguration, and networking monitoring of power...
This paper investigate the analysis of power and area of Advanced Encryption Standard (AES) algorithm using different design tool like ARM based, Hardware (VHDL/Verilog) and HW/SW. Results of area and power consumption for different design are varying and the percentage improvement in the power and area is marginable.The power improvement range is between 22.5% to 90% and the area improvement range...
Complex Event Processing (CEP) is an emerging field in high performance computing paradigm where real time (low latency) computing capability is expected over big data processing (high throughput). Significant number of software architectures have been developed to improve the throughput while reduce the latency but maintaining of the both aspects reaches the limits of the software platforms. This...
A high-performance interconnection between a host processor and FPGA accelerators is in much demand. Among various interconnection methods, a PCIe bus is an attractive choice for loosely coupled accelerators. Because there is no standard host-FPGA communication library, FPGA developers have to write significant amounts of PCIe related code at both the FPGA side and the host processor side. A high-performance...
In automotive electronics, the approach to integrate several existing single-core electronics control units into a multicore computer platform is now emerging. The integration may result in mixed-criticality systems where robust segregation between software applications is crucial. Another requirement for this process is the reusability of legacy software. Virtualization is a promising technique which...
Programming in embedded systems has always been a challenge. Highly-constrained nature of embedded devices invalidates conventional coding practices. The whole practice turns into a skill game that heavily depends on the personal skills and experience of the programmer. Embedded security applications are no exceptions. Efficient software implementation of symmetric cryptography primitives such as...
Generation of device-unique digital signatures using Physically Unclonable Functions (PUFs) is an active area of research for the last decade. However, most PUFs are conceived and designed as stand-alone hardware modules. In contrast, this paper proposes a PUF architecture that is tightly integrated into the core of a system-on-chip (SoC), with the purpose of creating a physical SoC authentication...
Creativity of a computer engineer is always sought after due to the increasing demands in the production of embedded systems worldwide. To ensure teaching of computer architecture subject as interesting as possible to computer engineering students, a simulation software for understanding typical computer processors was introduced. For hardware realization, a hardware description language was also...
Systemic Computation is an unconventional paradigm which defines a model of natural behavior and implies a massively parallel computer architecture. It is designed to be a computational paradigm for natural systems and processes modeling. Existing software implementations have been too limited in terms of performance, flexibility and programmability. This paper solves key problems that remained in...
Current High-Frequency Trading (HFT) platforms are typically implemented in software on computers with high-performance network adapters. The high and unpredictable latency of these systems has led the trading world to explore alternative "hybrid" architectures with hardware acceleration. In this paper, we survey existing solutions and describe how FPGAs are being used in electronic trading...
High Level Synthesis for System on Chip is a challenging way to cut off development time, while assuming a good level of performance. But the HLS tools are limited by the abstraction level of the description to perform some high level transforms. This paper evaluates the impact of such high level transforms for ASICs and softcores on FPGA. On the representative example of motion detection, we show...
This paper reports a successful demonstration of Pollard rho algorithm on a hardware-software co-integrated platform. It targets the Elliptic curve discrete logarithmic problem (ECDLP) for a NIST-standardized curve over 112- bit prime field. To the best of our knowledge, this is the first report on fully functional, demonstrated hardware-accelerated ECC cryptanalytic engine. Our implementation uses...
This paper introduces the structure of the experiment system for computer composition principle, which has been realized by making use of FPGA experimental instrument developed by ourselves and Quartus software. The design of experiment system for computer composition principle is analyzed in detail, including hardware design and software design. The hardware design mainly includes the fundamental...
With the increased complexity of FPGA, the process of debugging and verifying is to become the key portion of the FPGA design procedure. By concluding the applications of Virtual JTAG technology in an actual project, this paper has provided some ideas about how to use Virtual JTAG technology to do logical design and board-level debug. Facts have proved that the means based on Virtual JTAG and Tcl/Tk...
To meet the communications requirements of a wide band radar system, a HDLC controller based on FPGA was designed. The controller is set to idle mode when system reset or software reset occurs. The controller can be set to receiving or sending mode by software control. The special feature of the controller is especial low error rate and using very little hardware resource. Finally the controller was...
Traditional approaches to evaluating a system's vulnerability to Single Event Upsets (SEUs) require elaborate and costly radiation beam testing or time-consuming simulation. While beam testing represents definitive evidence of a processor's susceptibility to radiation-induced upsets, we believe that low-cost in-house bit error injection tests provide a valuable tool both in their own right and as...
As FPGA resources continue to increase, FPGAs present attractive features to the High Performance Computing community. These include the power-efficient computation and application-specific acceleration benefits, as well as tighter integration between compute and I/O resources. This paper considers the ability of an FPGA to address another, increasingly important, feature - resiliency. Specifically,...
Logic emulators are extensively used for research and educational purpose in the field of digital systems design. Development of programmable devices enabled hardware emulation of complex digital circuits and systems. Comparing to the traditional digital model simulation, the physical implementation of the circuit on the emulator platform enables real application research. There are a lot of commercial...
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