The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Modern ASIC and FPGA based embedded products use model based design, in which both hardware and software are developed in parallel. Previously HW was completed first and the information handed over to SW team, typically in the form of register tables. The information was even manually copied to SW code, making any changes error-prone and laborious. IP-XACT is the most feasible standard to model HW...
Post-silicon validation is the last level of inspecting the silicon before it is delivered to the customer. Automotive microcontrollers use Direct Memory Access (DMA) extensively in safety critical applications. This article explains how post-silicon validation can be improved to address the needs of the growing complexity of microcontrollers with a large number of Intellectual Property (IP). With...
Chip level Functional verification of processor based IC designs predominantly use directed test cases implemented in high level programming languages like "C". The verification test case software (SW) runs on the control core of the IC and configures different IPs to implement a particular functionality that verifies a set of functional requirements. Chip level verification environment...
The integration of mixed signal circuits in Systems on Chip is a trend in modern systems and applications with important challenges. In particular, the simulation of this kind of systems is a very time-consuming process that is becoming more and more complex due to the size of current designs. This paper describes a HW/SW co-simulation environment for mixed-signal circuits. The analog components are...
Heterogeneous multiprocessor SoCs (MPSoCs) are becoming very complex with greater demands for performance and low power. Advanced hardware techniques and involved software programming (>1000 registers) are employed to attain low/ultra-low power. Power management (PM) software development time is high. It is made worse with heavy rework when migrating across SoCs. In this paper we propose techniques...
The prevalent use of systems-on-chip (SoCs) makes them prime targets for software attacks. Proposed security countermeasures monitor software execution in real-time, but are impractical, and require impractical changes to the internal logic of intellectual property (IP) cores. We leverage the software observability provided by the readily available SoC debug architecture to detect attacks without...
We propose a communication architecture for EtherCAT master motivated by the technological progress in IT systems and Industrial Ethernet in control systems. In the proposed method, a dedicated hardware named the EtherCAT accelerator offers virtualized real-time and IT communication channels by operating automatic control frame generation, time synchronization protocol, and transmission scheduling...
Local area network is separated into some groups to ensure the security in company, university, and so on. This is generally implemented by using the function of a networking device. However, it is not easy for this method to change the network layout. In addition, there is a problem with compatibility of the device. This paper proposes a network system which has functions to group clients and to...
Current I/O devices communicate based on the PCIe protocol, and by default, all the traffic passes through the CPU-memory complex. However, this approach causes bottleneck in system throughput, which increases latency and power as the CPU processes device specific protocols to move data between I/O devices. This paper examines the cost of this centralized I/O approach and proposes a new method to...
Hardware IP design verification is performed using exhaustive random stimuli, while incorporating a coverage driven flow. On the other hand, system-on-chip (SoC) verification methodologies, sometimes, use a directed C-based verification approach to validate the functionality of the design. There is no significant randomization exercised in this process. Reuse of IP testbench components for SoC verification...
Fast startup of a subsystem, such as an image subsystem, is important in mobile smart devices because the startup time is directly related to the responsiveness of applications, such as a camera. This paper proposes a CPU switch method that offloads the long initialization phase from the subsystem to the fast main CPU in an application processor. By providing a consistent execution environment in...
End applications like automotive, mobile, industrial, communications and infrastructure require hardware architectures with multiple processing elements to reduce overall system cost and power. Typical hardware architectures consist of multiple processors to meet computational needs along with a rich set of peripherals to meet connectivity requirements. The complex interaction between the processing...
In order to dynamicly monitor and manage the working state of space science experiment payloads, the large volume of science data should be performed for real-time transmission. According to this requirement, the paper proposes a design scheme of main information network based on Ethernet. A microprocessor TMS320F2812 and the Ethernet interface chip KSZ8851 are applied to set up the Ethernet communication...
A high-performance interconnection between a host processor and FPGA accelerators is in much demand. Among various interconnection methods, a PCIe bus is an attractive choice for loosely coupled accelerators. Because there is no standard host-FPGA communication library, FPGA developers have to write significant amounts of PCIe related code at both the FPGA side and the host processor side. A high-performance...
In this paper, an FPGA-based traffic sign recognition system is introduced for driver assistance applications. The system incorporates two major operations, traffic sign detection and recognition. The algorithms presented include hue detection for potential sign detection, morphological filters for noise reduction, labeling and Hausdorff distance calculation for template recognition. A new hardware...
Multi field packet classification is the enabling function for many novel and emerging network applications. Exponential growth of Internet traffic and classification rule sets demand novel hardware based architectural approaches to packet classification. Even though this is an immensely studied area, packet classification that supports scalability in both line rates and rule sets is scarce. In this...
This paper deals with the design and development of a System on chip [SoC] based Onboard Computer [OBC] for future onboard space applications of Indian Space Research Organization [ISRO]. The System on Chip approach shall integrate processor core with associated peripherals, other standard cores like MIL-STD-1553B core, application specific low power digital and analog circuits on a monolithic mixed-signal...
Current High-Frequency Trading (HFT) platforms are typically implemented in software on computers with high-performance network adapters. The high and unpredictable latency of these systems has led the trading world to explore alternative "hybrid" architectures with hardware acceleration. In this paper, we survey existing solutions and describe how FPGAs are being used in electronic trading...
This paper shows a multi-purpose System-on-Chip (SoC) platform for rapid prototyping of computation and data intensive applications. The platform is composed of an Intellectual property (IP) modules resource library, a 2D mesh Network-on-Chip (NoC) as communication infrastructure which scales to an arbitrary number of resources, avoiding bus-based communication. A general scheme to plug any IP resource...
This paper presents a design method of three point temperature acquisition system based on Ethernet. and described the hardware and software design of system in detail. the hardware section mainly describes the principle and use of Ethernet controler DM9000A which is widely used in industry. The software part represents the structure and transplant of the open source TCP / IP protocol stack uIP 1...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.