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In this paper we present the design and implementation of TMbox: An MPSoC built to explore trade-offs in multicore design space and to evaluate parallel programming proposals such as Transactional Memory (TM). Our flexible system, comprised of MIPS R3000-compatible cores is easily modifiable to study different architecture, library and operating system extensions. For this paper we evaluate a 16-core...
Problems involving network design can be found in many real world applications such as power systems, vehicle routing, telecommunication networks, phylogenetic trees, among others. These problems involve thousands or millions of input variables and often need information and solution in real time. In general, they are computationally complex (NP-Hard). In this context, metaheuristics like evolutionary...
Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide different perspectives of a design, many require that the design be fully re-implemented for parameter modifications or do not allow the design to be run at full-speed. Designs are frequently first modeled using a high-level language then later...
The testing and verification technology for system HDL models, focused to the significant improvement of the quality of design components for digital systems on chips and reduction the development time (time-to-market) by using the simulation environment, testable analysis of the logical structure HDL-program and the optimal placement of assertion engine is proposed.
There is a critical need for design automation in micro architectural modelling and synthesis. One of the areas which lacks the necessary automation support is synthesis of instruction codes targeting various design optimality criteria. This paper aims to fill this gap by providing a formal method and software tool for synthesis of instruction codes given the description of a processor as a set of...
The coupling architecture containing an FPGA device and a microprocessor has been widely used to accelerate microprocessor execution. Therefore, there have been intensive researches about synthesizing high-level programming languages (HLL) such as C and C++ into HW in the high-level synthesis community in order to make the work of reconfiguring the FPGA easier. However, the difference in a calling...
This paper presents a detailed analysis of the efficiency of software-only techniques to mitigate SEU and SET in microprocessors. A set of well-known rules is presented and implemented automatically to transform an unprotected program into a hardened one. SEU and SET are injected in all sensitive areas of MIPS-based microprocessor architecture. The efficiency of each rule and a combination of them...
Escaped errors in released silicon are growing in number due to the increasing complexity of modern processor designs and shrinking production schedules. Worsening the problem are recent trends towards chip multiprocessors (CMPs) with complex and sometimes non-deterministic memory subsystems prone to subtle, devastating bugs. This deteriorating situation is causing a growing portion of the validation...
Due to increases in design complexity, routing a reset signal to all registers is becoming more difficult. One way to solve this problem is to reset only certain registers and rely on a software initialization sequence to reset other registers. This approach, however, may allow unknown values (also called X-values) in uninitialized registers to leak to other registers, leaving the design in a nondeterministic...
Hardware co-processors are used for accelerating specific compute-intensive tasks dedicated to video/audio codec, encryption/decryption, etc. Since many of these data-processing tasks already have efficient software algorithms, one could reuse those to synthesize the co-processor IPs. However, such software algorithms are usually sequential and written in C/C++. High-level Synthesis (HLS) helps in...
Traditional evolutionary algorithms require a lot of memory and processing power on embedded logic projects. Representing populations of candidate solutions through vectors of probabilities rather than sets of bit strings saves memory and processing. The concise evolutionary algorithm (CEA) is a probability vector based evolutionary algorithm. The article presents an FPEA realization of the standard...
Software chip is designed to present a study software platform without support of hardware entity by simulating hardware chip operating function. The paper introduces the concept of software chip, and presents software chip design methods. When designing a software chip, specific and related things or controls are chosen to substitute for the abstract functions of the chip, and signal flow trend and...
The NetFPGA platform is designed to enable students and researchers to build networking systems that run at line-rate, and to create re-usable designs to share with others. Our goal is to eventually create a thriving developer-community, where developers around the world contribute reusable modules and designs for the benefit of the community as a whole. To this end, we have created a repository of...
Based on the software ISE and EDK, a verification system of USB2.0 IP core which is designed in the authors' lab for system-on-a-chip (SoC) application is proposed. The top-level design is in the ISE and an embedded sub-module is included in the ISE top project. The C code for operating the IP core is also done. All the work is downloaded to FPGA board, so the correctness of the IP core is verified.
Nios II is the soft-core 32 bits RISC processor of the Altera Corporation which can be implied in its FPGA. Users can design their own peripherals accord with Avalon Bus specification in Nios II system. A new design method for plus width module (PWM) peripheral is presented, which is completed by Verilog HDL. Comparing to the common PWM module, this new PWM module use the hardware units (logic elements...
Multiprocessor system on chip (MPSoC) architecture is rapidly gaining momentum for modern embedded devices. The vulnerabilities in software on MPSoCs are often exploited to cause software attacks, which are the most common type of attacks on embedded systems. Therefore, we propose an MPSoC architectural framework, CUFFS, for an application specific instruction set processor (ASIP) design that has...
Sensor network nodes have a very tight power budget and the power efficiency is the biggest design concern in sensor network circuits. A general-purpose processor (e.g. an ARM processor) is not efficient to execute encryption algorithms because it has no special instructions to support encryption operations, for example very often-used permutation operations. In the paper, we propose a low-power ASIC...
This paper presents a configuration circuit used in the FDP (FDP: Fu Dan Programmable device) FPGA chip. This circuit could write configuration data into FDP and read back data from FDP successfully. Comparing with Xilinx Virtex Series FPGA chips, the smallest configuration section of which is one data-frame, the proposed circuit could write each single memory cell in FDP, providing more flexible...
Modern semiconductor designs include an incredible amount of embedded logic in the name of DFx (which is largely comprised of design-for-test, design-for-debug, and design-for-yield content and will be called "instruments" in this paper). Most of this logic has the IEEE 1149.1 (JTAG) Test Access Port (TAP) and the JTAG TAP Controller as its primary access mechanism or, if not the primary,...
An application-specific instruction-set processor (ASIP) is a technique that exploits special characteristics of application(s) to meet the desired performance, cost and power requirements. The generation and selection of Application-Specific Instructions (ASIs) dramatically affect the quality of an ASIP with design constraints such as number of register file I/Os and hardware cost. In this paper,...
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