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This paper presents a technique to integrate wireless field devices using WirelessHART and ISA100.11a technologies into a condition monitoring system based on Wonderware InTouch software. The proposed integration brings the data from a field site with digital multi-device networking for automatic data collection to support the condition monitoring of instruments or smart connected equipment in preparation...
Quantum computing promises new opportunities for solving hard computational problems, but harnessing this novelty requires breakthrough concepts in the design, operation, and application of computing systems. We define some of the challenges facing the development of quantum computing systems as well as software-based approaches that can be used to overcome these challenges. Following a brief overview...
This document presents the contents and didactic methodology followed through the Digital Electronics course, imparted during the fifth semester of the Grado en Ingeniería Electrónica Industrial y Automática (Rama Industrial) at Universidad de Extremadura. Lab sessions reinforce all the theory contents of the course, providing the student with the experience of designing a microprocessor (with didactic...
Heavy ion single-event effect (SEE) measurements on Xilinx Zynq-7000 are reported. Heavy ion susceptibility to Single-Event latchup (SEL), single event upsets (SEUs) of BRAM, configuration bits of FPGA and on chip memory (OCM) of the processor were investigated.
In this paper, an application-specific instruction-set processor (ASIP) implementation for interpolation operation for high efficiency video coding (HEVC) decoders is proposed. HEVC is a new video compression standard that has higher compression efficiency than the previous ones. The proposed ASIP is implemented on the XRC_D2MR processor by augmenting the instruction set architecture in Xtensa Tensilica...
In cloud computing, hypervisor is the all-powerful software running in the highest privilege layer, thus attackers who compromise a hypervisor may jeopardize the whole cloud, especially cause memory corruption of any sensitive workloads within the cloud. In this paper, we propose a novel architecture and approach to provide memory protection from an untrusted hypervisor on current x86 platforms. Unlike...
The computing demand of many signal processing algorithms is dramatically growing because of the increasing complexity of embedded software applications. Concurrently, as process technology scales, the design effort for realizing very large scale integrated circuits and the associated costs are becoming critically high. A possible solution to address this performance/costs challenge is given by customizable...
This paper discuss about a power management unit (PMU) which will be implemented in a modular hardware accelerator. The PMU aims to achieve power savings without significantly affecting the performance of the hardware accelerator by timely switching the power state of the device depending on the traffic accessing it and its operating state. The main methods used for power management would be clock...
Network protocols today play a major role in embedded software for industrial automation, with constant efforts to adapt existing device software to new emerging standards. In earlier work, we have proposed a compilation-based approach using a domain-specific language, Protege, which automatically generates protocol stack implementations in C from modular high-level descriptions. In this paper, we...
With the increasing complexity of integrated circuits and transition to Systems-on-Chip (SoC) paradigm, Automatic Test pattern Generation (ATPG) becomes a crucial tool in the Electronic Design Automation (EDA) domain. ATPG based on Boolean Satisfiability (SAT) has been proposed as an alternative to classical structural algorithms for generating test patterns for single stuck-at faults in combinational...
Logic circuit can be reduced, if any input is given as a constant. The derived circuit usually operates at a higher frequency, as the logic depth and layout area are reduced. Such technique is called as hardware specialization, since the circuit is specialized to specific input data. This study presents the quantitative evaluation results of hardware specialization for vibration control systems, using...
With the development of computer technology, embedded TCP/IP protocol stack has become an important part of the network information intelligence. Considering the structure features of the embedded TCP/IP protocol stack, this paper discusses the specific implementation procedure of the protocol stack network interface layer. The datagram module of RTL8019AS controller and the Ethernet data sending...
Due to increases in design complexity, routing a reset signal to all registers is becoming more difficult. One way to solve this problem is to reset only certain registers and rely on a software initialization sequence to reset other registers. This approach, however, may allow unknown values (also called X-values) in uninitialized registers to leak to other registers, leaving the design in a nondeterministic...
Hardware co-processors are used for accelerating specific compute-intensive tasks dedicated to video/audio codec, encryption/decryption, etc. Since many of these data-processing tasks already have efficient software algorithms, one could reuse those to synthesize the co-processor IPs. However, such software algorithms are usually sequential and written in C/C++. High-level Synthesis (HLS) helps in...
Instruction set simulators can be used for the early development and testing of software for a processor before it is manufactured. While gate-level simulation of the overall design offers cycle-accurate results, performance of the simulation is typically not sufficient for in-depth software testing. In addition, such a gate-level simulation cannot be carried out in the early phases of the design...
Test automation is facing a new challenge because tools, as well as having to provide conventional test functionalities, must be capable to interact with ever more heterogeneous complex systems under test (SUT). The number of existing software interfaces to access these systems is also a growing number. The problem cannot be analyzed only from a technical or engineering perspective; the economic perspective...
System on Chip (SOC) could be considered as a very useful alternative in the design of real-time systems, especially due to the possibility of integrating several processors in just one FPGA. This strategy enables the use of soft processors to design the systempsilas components, which have traditionally been developed by hardware. In this paper we study a HW/SW codesign of a timer pool for its use...
Modern semiconductor designs include an incredible amount of embedded logic in the name of DFx (which is largely comprised of design-for-test, design-for-debug, and design-for-yield content and will be called "instruments" in this paper). Most of this logic has the IEEE 1149.1 (JTAG) Test Access Port (TAP) and the JTAG TAP Controller as its primary access mechanism or, if not the primary,...
We present a practical, systematical method for the evaluation of the soft error rate (SER) of microelectronic devices. Existing methodologies, practices and tools are integrated in a common approach while highlighting the need for specific data or tools. The showcased method is particularly adapted for evaluating the SER of very complex microelectronic devices by engineers confronted to increasingly...
Field programmable gate arrays (FPGAs) are getting more and more attractive for military and aerospace applications, among others devices. The usage of non volatile FPGAs, like Flash-based ones, reduces permanent radiation effects but transient faults are still a concern. In this paper we propose a new methodology for effectively measuring the width of radiation-induced transient faults thus allowing...
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