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Traditional approaches to evaluating a system's vulnerability to Single Event Upsets (SEUs) require elaborate and costly radiation beam testing or time-consuming simulation. While beam testing represents definitive evidence of a processor's susceptibility to radiation-induced upsets, we believe that low-cost in-house bit error injection tests provide a valuable tool both in their own right and as...
In this paper we present the design and implementation of TMbox: An MPSoC built to explore trade-offs in multicore design space and to evaluate parallel programming proposals such as Transactional Memory (TM). Our flexible system, comprised of MIPS R3000-compatible cores is easily modifiable to study different architecture, library and operating system extensions. For this paper we evaluate a 16-core...
With the increasing complexity of integrated circuits and transition to Systems-on-Chip (SoC) paradigm, Automatic Test pattern Generation (ATPG) becomes a crucial tool in the Electronic Design Automation (EDA) domain. ATPG based on Boolean Satisfiability (SAT) has been proposed as an alternative to classical structural algorithms for generating test patterns for single stuck-at faults in combinational...
This paper proposes Flex Core, a hybrid processor architecture where an on-chip reconfigurable fabric (FPGA) is tightly coupled with the main processing core. Flex Core provides an efficient platform that can support a broad range of run-time monitoring and bookkeeping techniques. Unlike using custom hardware, which is more efficient but often extremely difficult and expensive to incorporate into...
The Multi-Protocol Multi-Band (MPMB) Software Defined Radio (SDR) devices require flexible as well as efficient physical layer (PHY) processing. We address an efficient implementation of flexible PHY for Interleaving and De-Interleaving operation through Application Specific Instruction Set Processors (ASIPs). We propose a multi-standard (802.11a, 802.16e/m) supporting Interleaver / De-Interleaver...
In this paper we describe a new generic approach for accelerating software functions using a reconfigurable device connected through a high-speed link to a general purpose system. As opposed to related ISA extension approaches, we insert system calls to the original program at hand to control the reconfigurable accelerator. The reconfigurable device is controlled by the host through a device driver,...
Current emerging reconfigurable coarse grained processors are gaining more popularity, as they introduce a new way for more dynamicity similar to FPGA and tend to achieve the performance of application specific hardware. An adaptive architecture can face the diversity of applications dynamically in the hardware without the need of any software manipulation. However the need for more flexibility to...
Hardware acceleration uses hardware to perform some software functions faster than it is possible on a processor. This paper proposes to optimize hardware acceleration using path-based scheduling algorithms derived from dataflow static scheduling, and from control-flow state machines. These techniques are applied to the MIPS-to-Verilog (M2V) compiler, which translates blocks of MIPS machine code into...
This paper introduces the specialization of a NIOS2 processor targeting the computation of message authentication codes and integrity checks in constrained environments. Several hardware/software partitioning levels are considered, which vary from simple functions implemented as custom instructions to complete algorithms as peripherals. Our experimental results show that functions Sum, Sig, Ch, Maj...
This paper presents the performance analysis hardware/software co-design of iterative methods for solving linear systems in terms of speed, iteration and toleration. Three iterative methods, Jacobi, Gauss-Seidel (GS) and conjugate gradient (CG), are implemented using Xilink EDK (embedded development kit). For comparison purposes, the same methods are also implemented in pure software using Xilink...
The SOBER family ciphers are widely used in embedded devices. For improving these cipherspsila processing speed, this paper introduces the reconfigurable processing architecture design for them. According to need, the reconfigurable processing architecture can implement SOBER, SOBER-II,S16,S32,SOBER t-class and SOBER-128 stream ciphers. The prototype of the reconfigurable processing architecture has...
As FPGA devices become larger, more coarse-grain modules coupled with large scale reconfigurable fabric become available, thus enabling new classes of applications to run efficiently, as compared to a general-purpose computer. This paper presents an architecture that benefits from the large number of DSP modules in Xilinx technology to implement massive floating point arithmetic. Our architecture...
Adaptive systems are set to become more mainstream, as numerous practical applications in the communications domain emerge. FPGAs offer an ideal implementation platform, combining high performance with flexibility. While significant research has been undertaken in the area of FPGA partial reconfiguration, it has focussed primarily on low-level architecture-specific implementations. Building upon this...
This paper presents the architectural design of a reconfigurable and extensible very long instruction word (VLIW) processor. In addition to architectural extensibility, our processor also supports reconfigurable operations. Furthermore, we present an application development framework to optimally exploit the freedom of reconfigurable operations. Because our processor is based on the VEX ISA, we already...
Adaptive computers combine conventional software programmable processors with reconfigurable compute units. We present techniques that allow the high-performance realization of demand-paged, virtually addressed main memory shared between both of these processing elements. Furthermore, we have achieved low-latency communication between software running on the CPU and the reconfigurable compute unit,...
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