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Data processing and combinatorial search are widely used techniques in the scope of information and communication. Examples of practical applications are sorting, frequent items encountering, matrix/set covering, graph/map coloring, data mining, priority management, and many others. Often information/data processing that involves the listed above tasks has to be done in embedded systems where high...
Hardware IP design verification is performed using exhaustive random stimuli, while incorporating a coverage driven flow. On the other hand, system-on-chip (SoC) verification methodologies, sometimes, use a directed C-based verification approach to validate the functionality of the design. There is no significant randomization exercised in this process. Reuse of IP testbench components for SoC verification...
End applications like automotive, mobile, industrial, communications and infrastructure require hardware architectures with multiple processing elements to reduce overall system cost and power. Typical hardware architectures consist of multiple processors to meet computational needs along with a rich set of peripherals to meet connectivity requirements. The complex interaction between the processing...
A complete framework and methodology to design, simulate, and debug large SoC is presented. Full VP creation using efficient tools is described. An efficient tool to allow co-debug of HW/SW on VP is also presented. The tools enable debugging and analyzing an application and a Linux driver that run on the VP. Breakpoints and mon commands can be used to detect and correct errors, access registers and...
Common way for IP-Core standalone verification assumes UVM based environments and tests development. At the same time, IP-core integration verification at the SoC level and hardware-software co-verification as a whole, requires development of the code running on the embedded CPU (usually written on C/C++). When C/C++ tests and software are developed it is desirable to reuse IP-Core standalone level...
This paper proposes a hardware fault detection approach by using redundancy core for Multiprocessor system-on-chip (MPSoC). The proposed approach insert some error detection code in high level code and remove the calculation of detection code to the redundancy core of MPSoC. The author compares the proposed approach with several soft-based fault detection methods on fault detection capabilities, area,...
This paper deals with the design and development of a System on chip [SoC] based Onboard Computer [OBC] for future onboard space applications of Indian Space Research Organization [ISRO]. The System on Chip approach shall integrate processor core with associated peripherals, other standard cores like MIL-STD-1553B core, application specific low power digital and analog circuits on a monolithic mixed-signal...
Traditional approaches to evaluating a system's vulnerability to Single Event Upsets (SEUs) require elaborate and costly radiation beam testing or time-consuming simulation. While beam testing represents definitive evidence of a processor's susceptibility to radiation-induced upsets, we believe that low-cost in-house bit error injection tests provide a valuable tool both in their own right and as...
In this paper we present the design and implementation of TMbox: An MPSoC built to explore trade-offs in multicore design space and to evaluate parallel programming proposals such as Transactional Memory (TM). Our flexible system, comprised of MIPS R3000-compatible cores is easily modifiable to study different architecture, library and operating system extensions. For this paper we evaluate a 16-core...
With the increasing complexity of integrated circuits and transition to Systems-on-Chip (SoC) paradigm, Automatic Test pattern Generation (ATPG) becomes a crucial tool in the Electronic Design Automation (EDA) domain. ATPG based on Boolean Satisfiability (SAT) has been proposed as an alternative to classical structural algorithms for generating test patterns for single stuck-at faults in combinational...
Assessing and improving the level of system robustness with respect to soft errors has become one of the main design challenges, especially when designing critical embedded systems. In systems using microprocessors (e.g. most of SoCs) the system dependability is strongly correlated with the variable lifetimes. In this paper, we discuss the impact of compilation optimizations on the lifetimes in both...
The Multi-Protocol Multi-Band (MPMB) Software Defined Radio (SDR) devices require flexible as well as efficient physical layer (PHY) processing. We address an efficient implementation of flexible PHY for Interleaving and De-Interleaving operation through Application Specific Instruction Set Processors (ASIPs). We propose a multi-standard (802.11a, 802.16e/m) supporting Interleaver / De-Interleaver...
In this paper, we present the design of a baseband System-On-Chip for tracking applications in the medical environment based on the IEEE 802.15.4 standard which can be used to track patient location in hospitals. It utilizes an ARM Cortex-M1 soft-core, 16 kb of SRAM and a bus architecture based on the AHB-Lite specification. The IEEE 802.15.4 MAC primitives are implemented in a Flash-ROM of 32 kb...
The testing and verification technology for system HDL models, focused to the significant improvement of the quality of design components for digital systems on chips and reduction the development time (time-to-market) by using the simulation environment, testable analysis of the logical structure HDL-program and the optimal placement of assertion engine is proposed.
The testing and verification technology for system HDL models, focused to the significant improvement of the quality of design components for digital systems on chips and reduction the development time (time-to-market) by using the simulation environment, testable analysis of the logical structure HDL-program and the optimal placement of assertion engine is proposed.
Due to the continuously decreasing cost of FPGAs, they have become a valid implementation platform for SOCs. Typically, a soft core processor implementation is used to execute the software parts of the SOC. As each system is individually designed for a particular application, the idea is natural to support compute intensive parts of the code through customized hardware acceleration. Two different...
The testing and verification technology for system HDL models, focused to the significant improvement of the quality of design components for digital systems on chips and reduction the development time (time-to-market) by using the simulation environment, testable analysis of the logical structure HDL-program and the optimal placement of assertion engine is proposed.
This study develops and implements a SoC-based HW/SW (Hardware-Software) codesign for an intelligent diagnostic system. To improve the efficiency of the VLSI (Very Large Scale Integration) design process, the components of the intelligent diagnostic system are designed in the form of SIP (Silicon Intellectual Property) modules. The SIP modules, including the CPU module, the GPIO (General Purpose I/O)...
Recent trends of hardware intellectual property (IP) piracy and reverse engineering pose major business and security concerns to an IP-based system-on-chip (SoC) design flow. In this paper, we propose a Register Transfer Level (RTL) hardware IP protection technique based on low-overhead key-based obfuscation of control and data flow. The basic idea is to transform the RTL core into control and data...
The solution to debug a problem in a deeply embedded system is to integrate the debug and communication module inside the chip. In this paper, we propose an on-chip in-circuit emulation (ICE) architecture for debugging an asynchronous Java accelerator core which can be integrated with any existing processor and operating system. The operation of this ICE module and the debug strategy of the Java accelerator...
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