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In this paper, we have presented a design of hybrid arithmetic logic unit (ALU) in Double precision format (DPF) according to the IEEE-754 standard. In this we have designed an ALU which consists of the two different architectures. First architecture is semi-floating point unit (Semi-FPU) and the second architecture is floating point unit (FPU). Semi-FPU takes a 32-bit integer input and produces an...
A new architecture for detecting sign bit in digital signal processing applications using the residue number system (RNS) is detailed. The utilization of residue number system (RNS) to digital signal processing lies in the capacity to work on signed numbers. Two troublesome calculations are identifying sign and compare the magnitude in RNS system. The design is based on using a restricted moduli set...
Implementation of filter needs mainly three basic building blocks as multiplier, adder and signal delay. If a filter has to be speed means it should have high speed basic building block i.e. multiplier and adder blocks should be very high speed. The paper presents a proposed digital FIR filter which is delay efficient and area efficient. The improvement of proposed Direct Form FIR filter in delay...
In this work, a novel architecture of Secure Hash Algorithm-1(SHA-1) for increased throughput and reduced area is presented. Various acceleration techniques are applied such as pre-computation, loop unfolding, and pipelining simultaneously. Carry Save Adder using Carry Lookahead Adder in its final stage is used for multi-input addition function to achieve high performance. The proposed architecture...
Now a days, low power Very Large Scale Integration (VLSI) circuit plays an important role in designing efficient energy saving electronic systems for high speed performance. In VLSI, low power dissipation is the main criterion in many electronic devices out of speed, area, etc., like mobile phones, laptops, high speed work stations etc., Due to the integration of many components on the VLSI circuit...
Addition is the most widely utilized arithmetic operations in any adder circuits. The performance of an adder is a speed determining factor for arithmetic operations. This project is proposed to analyse and compare the performance of various adder circuits in order to obtain the design of a high throughput aging-aware variable latency multiplier. The moderate performance degradation is achieved in...
Multipliers are the most important block in any arithmetic and logic unit, accumulators and Digital signal processors. Due to the increasing constraints on delay, design of faster multipliers is emphasized. Among several multipliers, Vedic multipliers are preferred for their speed of operation. Among the sixteen sutras in Vedic multiplication techniques our proposed “URDHVA TIRYAKBHYAM” a most efficient...
This paper proposes a novel methodology for design and multiplierless implementation of fractional order integrator (FOI) based on lattice wave digital filter using gravitational search algorithm (GSA). The FOI design problem is formulated as an optimization problem using the transfer function of lattice wave digital filter (LWDF). The realization of FOI using LWDF structure increases the accuracy...
This brief presents an efficient adaptive Reversible Logic Finite Impulse Response filter (RLFIR) based on Distributed Arithmetic (DA) using Reversible gates. Reversible logic is one of the most essential issues at present time due to its power reduction effectiveness in circuit designing. The delay and the logical resources of the proposed design were significantly reduced by using add one carry...
There are different entities that one would like to optimize when designing a VLSI circuit. The design of an efficient integrated circuit in terms of power, area, and speed simultaneously, has become a very challenging problem. Finite Impulse Response filters are the lead for DSP applications and communication. FIR filters has the multipliers of its heart of the system. So the improvement in the multiplier...
Finite Impulse Response filters are the most important element in signal processing and communication. FIR filter architecture has multiplier, adder and delay unit. So FIR filter performance is mainly based on multiplier. In this paper presents FIR filter implantation of Booth multiplier using Modified Carry Save Adder (MCSA) and Carry Save Adder (CSA). These techniques are used to improve the performance...
Modular multiplication finds the major role in RSA Cryptography and Elliptical Curve Cryptography. Timing analysis measures the delay along the various timing paths and verifies the performance and operation of the design. We have implemented a 256-bit Modular multiplier using Montgomery Reduction Algorithm in VHDL. The output of the Montgomery multiplier is Z=X∗Y R−1 mod M. Both RSA key generation...
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