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This paper presents a floating point arithmetic modules which are useful for many real time applications such as FFT processor where complex butterfly operations are performed, in which precision and accuracy play a pivotal role in bio-medical and signal processing applications. When compared to fixed point representation, floating point arithmetic provides high precision which helps in increasing...
This paper presents the use of one hot residue (OHR) number system (NS) for digital signal processing and designing of arithmetic circuits for high speed and low power applications. The best highlight of this scheme is that the delay of implementation is equal to delay of a transistor which has proved to be a good improvement in comparison to conventional methods. The other advantages of using residue...
In FFT computation, the butterflies play a central role, since they allow the calculation of complex terms. Therefore, the optimization of the butterfly can contribute for the power reduction in FFT architectures. In this paper we exploit different addition schemes in order to improve the efficiency of 16 bit-width radix-2 and radix-4 FFT butterflies. Combinations of simultaneous addition of three...
In the FFT computation, the butterflies play a central role, since they allow calculation of complex terms. In this calculation, involving multiplications of input data with appropriate coefficients, the optimization of the butterfly can contribute for the reduction of power consumption of FFT architectures. In this paper different and dedicated structures for the 16 bit-width radix-2 and radix-4...
At present scenario Polynomial basis multipliers are used because they are relatively simple to design, and offer scalability for the fields of higher orders. It is used in Cryptographic and FFT applications for secure data encryption and decryption which deals with discrete structure and mathematical arithmetic. Since it uses modular arithmetic operation, it is found that it has the latency of m...
This paper present a design of Fast Fourier Transform (FFT) processor for high speed DSP application like OFDM based communication systems such as digital audio and video broadcasting (DAB & DVB), asymmetric digital subscriber loop (ADSL), where the basic need of this type of application is high speed processing on data. We designed high speed FFT processor with pipelined architecture which is...
Different approaches for implementing a complex multiplier in pipelined FFT are considered and implemented to find an efficient one in this paper. The design is implemented in VHDL and design is synthesized on FPGA to know the performance. The design is implemented with a focus of reducing the resources used. Some approaches resulted in the reduced number of DSP blocks and others resulted in reduced...
To overcome the influence of Doppler shifts for the acquisition time of navigation receiver in high dynamic situation, a improved method adopts an acquisition algorithm composed of Partial Matched Filter (PMF) and Fast Fourier Transform (FFT) method. The algorithm changes the traditional two-dimensional searching strategy based on spread spectrum code phase and signal-carrier frequency into one-dimensional...
Fast Fourier Transform (FFT) processors, having a significant impact on the performance of communication systems, have been a hot topic of research for many years. FFT function consists of consecutive multiply-add operations over complex numbers, dubbed as butterfly units. Use of redundant number systems is a way of increasing the speed of FFT coprocessors. It eliminates carry-propagation and hence...
This paper describes the design and implementation of user defined fused floating-point arithmetic operations that can be used to implement Radix 2 Fast Fourier Transform (FFT) for complex numbers used in Digital Signal Processing (DSP-C) processors. The design is implemented and simulated by targeting Xilinx vertex 5 FPGA device. This paper describes the optimization of fused floating point modules...
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