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Parallel FIR filter is widely used among various types of filter in Digital Signal Processing (DSP). This paper shows the design of area-efficient 2-parallel FIR filter using VHDL and its implementation on FPGA using image system. This paper gives the details basic blocks of area-efficient 2-parallel FIR digital filter. In this paper proposed 2-parallel digital FIR filter and area-efficient 2-parallel...
This paper presents carry-lookahead adder (CLA) based design of the contemporary inexact-speculative adder (ISA) which is fine grain pipelined to include few logic gates along its critical path and thereby, enhancing the frequency of operation. Additionally, various stages of the proposed ISA architecture has been clock gated to reduce the power consumed by this design. Functional verification and...
This paper presents the concept, traits, principle and structure of 64-bit high speed VLIW microprocessor. The microprocessor facilitates 16 kinds of operational function. Out of these, our main focus is on the add operation. The add operation is implemented using 64-bit adders namely, Carry Look-ahead Adder, Carry Select Adder, Ripple Carry Adder, Weinberger Adder, Ling Adder and Modified CSLA using...
Performance of adders has a tremendous impact on system-level functionality especially in signal processing applications. Carry Select Adder (CSLA) is one such adder which is proved to be a high speed version among other conventional adders. This paper presents a novel architecture for SQRT-CSLA with modified ripple carry adder chain. The pivotal feature of the proposed architecture is that the final-sum...
In the Modern computers for performing the operationof ALU (Arithmetic Logic Unit) like Addition, Subtraction, different types of adders are using for achieving low delay and fastoutput. QSD numbers are using for giving the carry-free additionso that ALU operations can perform in low delay and speed of themodern computer can increase. In the modern digital system fastadder, Subtraction can perform...
Image compression and size reduction increases the number of images stored on a memory space and reduces bandwidth consumption while increasing transmission speed on a communication channel. Images can be compressed and decompressed using different methods and algorithms. With the vast increase of quality and size, dedicated processors with parallel processing blocks such as FPGAs are mainly targeted...
This paper presents a 65nm ASIC based 256 NIST prime field ECC processor. To achieve high throughput, extensive pipelining techniques were applied to realize the Karatsuba-Ofman Multiplier along with enhanced NIST Reduction Formula. The processor architecture was implemented using Global Foundry 65nm Low Power (LPE) technology. The processor runs at a maximum frequency of 244 MHz and performs single...
Novel methods for unauthorized access are always made. For cyber security measures in mobile devices, low-power and high-speed processing is very important. Despite these situations, a CPU for mobile devices is a very low processing capacity in order to focus on low-power operations and does not have sufficient performance for processing detection processing for unauthorized access. In contrast, a...
This work presents the implementation of operant conditioning (OC) and classical conditioning (CC) with a single spiking neural network (SNN) architecture, thus suggesting that the two types of leaning may relate to the same cognitive process. Both are achieved by using a modified version of spike-timing-dependent plasticity (STDP), where the connection weight between a cue neuron and an action neuron...
A multiplier requires an Adder circuitry to add carry of previous result to next stage to form partial products and to get final result of multiplication. This paper presents a novel way to implement Line Multiplier without using Adders. The Adder-less Multiplier is implemented on both CMOS and FPGA platforms. In ASIC paradigm CMOS 90nm technology and on FPGA platforms Spartan-3 have been used for...
In this paper, an architecture is proposed to calculate the histogram of image. Which is faster than the previousserial methods, this architecture achieves the parallelism butneeds the enough resources and gives the better performance. If, resources is not an issue then this is one of the best methodfor histogram calculation in FPGA (Field Programmable GateArray). Some other methods are also proposed...
This paper presents the fast carry chain adder using Instantiation design entry which facilitates the direct design of the components through exact placement of the individual blocks in FPGA. The basic n-bit adder is divided into n/3 number of ripple carry adders with carry inputs generated from separate carry generator. The carry generator is designed on LUT by using all the six inputs with 100%...
Complex numbers multiplication is a key arithmetic operation to be performed with high speed and less consumption of power in high performance systems such as wireless communications. Hence, in this paper, two possible architectures are proposed for a Vedic real multiplier based on the URDHVA TIRYAKBHYAM (Vertically and cross wise) sutra of Indian Vedic mathematics and an expression for path delay...
The proposed multiplier pertaining to concepts of Vedic Mathematics was designed to reduce propagation delay, design complexity as well as to optimize power consumption in comparison to conventional multipliers. A multiplier is a key element in DSP systems, serving as a building block of most computational digital systems, therefore, speed and power consumption are two important parameters of design...
Whilst the pre-fabricated aspects of FPGAs have many advantages, the fixed nature of the underlying fabric limits the optimized synthesis of arithmetic circuits on these platforms. Many adder architectures, that suit ASICs have been implemented using FPGAs and it has long been established that for FPGAs the ripple carry adder gives the best performance in terms of speed and resource utilization. This...
Modulo (231-1) adder is one of the important module in ZUC stream cipher. The paper presents compact, high performance architecture for modulo (231-1) adder using CLA. The proposed architecture is implemented by using VHDL language with CAD tool Xilinx ISE Design Suite 13.2 and target device is Xilinx Spartan3-xc3s1000, with package FG320. Presented result shows that proposed architecture minimizes...
In arithmetic operation, adder is the basic hardware unit. So adder performance affects the overall system-performance. Carry Select Adder (CSLA) is widely used in many data processors for high speed application and in digital circuits to perform arithmetic operations. The Regular Square root (SQRT) CSLA consumes more area due to the presence of two Ripple Carry Adders (RCA) in the structure. To optimize...
Arithmetic Logic Units are one of the vital unit in general purpose processors and major source of power dissipation. In this paper we have demonstrated an optimized Arithmetic and Logic Unit through the use of an optimized carry select adder. Carry select adders have been considered as the best in their category in terms of power and delay. In this context a full adder optimized in terms of power...
This paper address the issues involved in physical modelling synthesis using digital waveguides and its implementation in the hardware. Physical modelling of a one-dimensional musical resonator such as a string can be derived using digital waveguide modelling. The digital waveguide model itself comprises of pair of delay lines. This research models the string digital waveguide using an IIR filter...
Binary multiplication is an important operation in many high power computing applications and floating point multiplier designs. And also multiplication is the most time, area and power consuming operation. This paper proposes an efficient method for unsigned binary multiplication which gives a better implementation in terms of delay and area. A combination of Karatsuba algorithm and Urdhva-Tiryagbhyam...
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