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This paper makes a comparison between various quasi-delay-insensitive (QDI) asynchronous ripple carry adders (RCAs) realized using a delay-insensitive dual-rail code which correspond to 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The QDI RCAs considered are 32-bits in size and correspond to a variety of timing regimes viz. strong-indication, weak-indication, early output,...
In the recent days Fast Adders are implemented to increase speed, reduce delay, besides being cost effective. Several architectures and implementations of binary adders, gates, etc. were used in the past. But it was leading to complexity of the structure and also obscurity in implementation. In the proposed research paper implementation of Carry Look-ahead Adder (CLA) using Fast Adder for signal processing...
Vedic maths based multiplier is a novel and high speed multiplier. Adder is one of the main components used in this technique. Using fast adder will enhance the overall performance of the Vedic multiplier. In this work, comparative analysis is done using different adder architectures in Synopsis Design Compiler with different standard cell libraries at 32/28 nm. Various Adder topologies like Ripple...
Arithmetic adder is the most important basic element for many digital applications. In this paper different types of adders are taken for experimental study such as Ripple Carry Adder, Carry Save adder, Carry Look ahead adder, Carry Increment adder, Carry Select adder, and Carry Skip adder. Here in this paper introducing a novel technique for designing a new Carry Select adder for multi precision...
Multipliers are the key components of systems viz. FIR filters, Microprocessors, Digital Signal Processors etc. which demands high performance. The performance of these applications mainly depends on the numbers of multiplication done in unit time. In real time multipliers the speed and power are the major criteria, thus faster and power efficient multipliers are needed. This paper focuses on the...
This work synthesises high performance integer multiplier designs suitable for high speed reconfigurable VLS I systems. Various designs of integer multipliers are taken and are compared on the basis of area and speed and the design most suited for the given FPGA platform is understood. The designs are implemented on Virtex FPGA and the comparisons in terms of area and speed are made. The multiplier...
Addition is the fundamental operation used in computer arithmetic circuits and CMOS adder is the basic component of these systems. This paper presents the designs of new 4-bit and 8-bit split-path Data Driven Dynamic logic (sp-D3L) ripple carry adder (RCA) circuit. Power consumption of proposed 4-bit RCA's varies from 0.69nW to 2.75nW with variation in supply voltage from 1.8V to 3.3V. Maximum output...
This paper presents a MOS current mode logic (MCML) square root carry select adder (SQ-CSA) which can be used as an alternative to MCML ripple carry adder (RCA) when the number of bits in the input words is large. The proposed 16-bit MCML SQ-CSA has been implemented and simulated in PSPICE using TSMC 180 nm CMOS technology parameters. Its performance has been compared with 16-bit RCAs based on CMOS...
This paper proposes a Low-Power, Energy Efficient 4bit Binary Coded Decimal (BCD) adder design where the conventional 4-bit BCD adder has been modified with the Clock Gated Power Gating Technique. Moreover, the concept of DVT (Dual-vth) scheme has been introduced while designing the full adder blocks to reduce the Leakage Power, as well as, to maintain the overall performance of the entire circuit...
Subthreshold design has been proposed in the literature as an effective technique for designing signal processing circuits needed in wireless body area network (WBAN) powered by sources with limited energy. The full adder cell forms the basic building block of majority of these signal processing circuits. In this paper, 8-Bit subthreshold Ripple Carry Adders (RCAs) for wireless sensor nodes optimized...
Higher operating frequencies may be obtained in digital systems by using wave-pipelining which permits clock frequencies higher that dictated by largest propagation delay between input and output. This, however, requires proper selection of clock periods and clock skews so as to latch the output of combinational logic circuits at the stable periods. In the literature, only trial and error and manual...
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