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A new technique of Ripple carry adder using majority gate based CMOS output wired logic is implemented. The ripple carry adder consists of four Full adder blocks. The carry from each stage is fed to the next stage as carry input. The Sum and carry outputs are obtained using output wired CMOS logic based majority gate. The number of transistors used in the proposed circuit design is less as compared...
In this paper, we have presented a design of hybrid arithmetic logic unit (ALU) in Double precision format (DPF) according to the IEEE-754 standard. In this we have designed an ALU which consists of the two different architectures. First architecture is semi-floating point unit (Semi-FPU) and the second architecture is floating point unit (FPU). Semi-FPU takes a 32-bit integer input and produces an...
One of the most crucial components in the computing devices is the full adders. The efficiency and effectiveness of arrays of full adders is essential; thus making it sensible to put in a reasonable effort towards improvisation of computational devices. In this paper, a new 1-BIT Full Adder (FA) with a combination of pass transistor logic and transmission gate logic is suggested. This new hybrid adder...
Null Conventional Logic (NCL) is one of the most robust design techniques amongst the other asynchronous design methodologies. The NCL circuits which follow Dual-rail logic are built from a library of 27 Threshold gates which are implemented using semi-static implementation. In this paper 1-bit, 4-bit and 8-bit NCL Ripple Carry Adders have been designed and compared with the corresponding Ripple Carry...
Memristors are non-volatile memory elements. In applications like mem-computing, where memory acts both as a site for storing data and logic computations, memristors provide promising future. In this paper, the design of adders implemented with memristors is discussed. Memristor based designs for standard fixed point adder architectures (ripple carry adder, carry look-ahead adder and parallel prefix...
VLSI technology is an emerging field in the current technological scenario due to its advancements in fields of systems architecture, analog and digital logic and adders are the basic building blocks in digital integrated circuit based designs. The existing Ripple Carry Adder (RCA) has the most compact design but takes longer computation time. The time critical applications use Carry Look-ahead Adder...
This paper presents the fast carry chain adder using Instantiation design entry which facilitates the direct design of the components through exact placement of the individual blocks in FPGA. The basic n-bit adder is divided into n/3 number of ripple carry adders with carry inputs generated from separate carry generator. The carry generator is designed on LUT by using all the six inputs with 100%...
Adders are digital components which are widely in the digital integrated circuit design and are the important part of all digital applications like Digital Signal Processing (DSP), microprocessor applications. As the technology is scaling down, researchers are trying to design adders which are either high speed, low power consumption, less area. In this paper, the design of Ripple Carry Adder are...
The proposed multiplier pertaining to concepts of Vedic Mathematics was designed to reduce propagation delay, design complexity as well as to optimize power consumption in comparison to conventional multipliers. A multiplier is a key element in DSP systems, serving as a building block of most computational digital systems, therefore, speed and power consumption are two important parameters of design...
Vedic multiplier is an efficient system for faster result and optimized circuit design. Maintaining higher throughput in arithmetic operations is important to achieve the desired performance in many real-time applications. One of the key arithmetic operations in such applications is to achieve faster multiplication. Vedic Mathematics is one of the fast and low power multiplier. In the present paper,...
In this paper, area-efficient Vedic multiplier is designed using modified Carry Select Adder (CSLA). As the multiplication is nothing but subsequent addition process, adder is important block in the design of multiplier. Simple Ripple Carry adder (RCA) can be used for implementing multiplier. Digital adder has problem of carry propagation, thus carry select adder is used instead. Carry select adder...
In this paper, the design and comparative analysis is done in between the most well-known column compression multipliers by Wallace [5] and Dadda [6] in sub-threshold regime. In order to reduce the hardware which ultimately reduces an area and power, energy efficient basic modules AND gates, half adders, full adders and partial product generate units have been analyzed. At the last stage ripple carry...
The constant delay (CD) logic makes high speed operation of the dynamic circuits possible. In the CD logic, the timing block plays a vital role as it helps in reduction of the evaluation time, by defining a small window width. This paper proposes a modified timing block which yields minimized area even while accomplishing the function. Use of the CD logic across cascaded stages employing the proposed...
In this paper a novel, low-latency family of high-radix Parallel Prefix Network adders and modular adders has been proposed. This family efficiently takes advantage of fast carry chains of modern FPGAs. The implementation results reveal that these adders have great potential for efficient implementation of modular addition with the long integers used in various public key cryptography schemes.
In this paper, a high speed and low power 16×16 Vedic Multiplier is designed by using low power and high speed modified carry select adder. Modified Carry Select Adder employs a newly incremented circuit in the intermediate stages of the Carry Select Adder (CSA) which is known to be the fastest adder among the conventional adder structures. A Novel technique for digit multiplication namely Vedic multiplication...
Subthreshold design has been proposed in the literature as an effective technique for designing signal processing circuits needed in wireless body area network (WBAN) powered by sources with limited energy. The full adder cell forms the basic building block of majority of these signal processing circuits. In this paper, 8-Bit subthreshold Ripple Carry Adders (RCAs) for wireless sensor nodes optimized...
Higher operating frequencies may be obtained in digital systems by using wave-pipelining which permits clock frequencies higher that dictated by largest propagation delay between input and output. This, however, requires proper selection of clock periods and clock skews so as to latch the output of combinational logic circuits at the stable periods. In the literature, only trial and error and manual...
A novel Chinese abacus adder is presented in this paper. The simulation results of 8-bit adders are compared with those of CLA (carry look-ahead) adder and RCA (ripple carry adder) by all input patterns. The delay of the 8-bit abacus adder is 22%, and 14% less than those of CLA adders for 0.35mum and 0.18mum technologies, respectively. The power consumption of the abacus adders are 30% and 60% less...
An approach to designing CMOS adders for both high speed and low power is presented by analyzing the performance of three types of adders - linear time adders, logN time adders and constant time adders. The representative adders used are a ripple carry adder, a blocked carry lookahead adder and several signed-digit adders, respectively. Some of the tradeoffs that are possible during the logic design...
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