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This paper presents the design of a rounded, truncated hybrid multiplier. The maximum absolute error is ensured to be less than one unit of least position. The proposed strategy includes deletion, reduction of partial product bits of multiplier in order to reduce the number of full adders and half adders used during partial product reduction. The high speed computing system requires high-speed and...
Any signal processing architecture has a multiplier as its pillar. Its computational capabilities depend on the multiplier's performance. Also, low-power designs are the need of next generation processors. Reversible logic is one of the promising future low power technologies. High-speed multiplication can be achieved if the carry-propagation is faster. Digital compressors have less latency in carry-propagation...
Vedic maths based multiplier is a novel and high speed multiplier. Adder is one of the main components used in this technique. Using fast adder will enhance the overall performance of the Vedic multiplier. In this work, comparative analysis is done using different adder architectures in Synopsis Design Compiler with different standard cell libraries at 32/28 nm. Various Adder topologies like Ripple...
Compressors form the basic element of arithmetic circuits that are dominated by multi-operand addition operations. Compressor circuits based on carry-save logic have been used in past to realize parallel multipliers for ASIC implementation, however, owing to the peculiar architecture of FPGAs, these circuits do not map well on these platforms. In this paper, FPGA implementation of 4:2 compressor circuit...
Booth multiplier is a multiplication of two binary numbers in two's complement notation and the proposed project new technique introduced i.e. fixed width multiplier is part of booth multiplier, in this 5-2 compressor is used with pipelining so that it leads to decrease the absolute error and improve the accuracy and delay also less. Unlike previous conditional-probability methods, the proposed Multi...
The main objective of this concept is to design a memory efficient FFT processor with low power consumption. Enhanced memory addressing scheme is proposed to deal with these complex and higher radix FFT processors. Dual port merged bank memory is designed in-order to deal with memory based FFT processors. Each and every butterfly unit needs one memory to store those computational permutations. So,...
Multipliers are major blocks in the most of the digital and high performance systems such as Microprocessors, Signal processing Circuits, FIR filters etc. In the present scenario, Fast multipliers with less power consumption are leading with their performance. Wallace tree multiplier with carry select adder (CSLA) is one of the fastest multiplier but utilizes more area. To improve the performance...
In digital VLSI circuits, perfectly accurate outputs are not always needed. So designers have started to design error tolerance circuits which provide good enough output for computation. On the basis of this fact, error tolerant adder (ETA) is designed which provides a way to achieve good power and speed performance. In this paper, an emerging logic style of circuit design, gate diffusion input (GDI)...
Modern day technology has extended its reach below 20 nm. All kinds of effects are to be seen in MOS devices due to different leakage mechanisms at deep sub-micron levels. These lead to errors in the system. Error tolerance (ET), an emerging concept in the field of VLSI design and test: by easing the restriction on accuracy, can be used to have improvements in speed and power depending on the amount...
Low-power is indispensable for the design of an efficient DSP system which is employed in many multimedia applications. Infinite Impulse Response (IIR) filter is an imperative requirement in the design of several such Digital Signal Processing (DSP) applications, such as, image processing, video compressions and Radar. The output of these applications which is either an image or a video can be justaccurate...
Achieving high speed integrated circuits with low power consumption is a major concern for the VLSI circuit designers. Most arithmetic operations are done using multiplier, which is the major power consuming element in the digital circuits. Basically the process of multiplication is realized in hardware in terms of shift and add operation. The optimization of adder has led to the improvement in performance...
Signal processing requires high performance digital signal processors(DSP) and hardware accelerators. Real and complex multiply-accumulate(MAC) units are the most critical computation units in the DSPs and accelerators, which greatly impact the performance, power and chip area of the signal processing system. A fixed-point Single-Instruction-Multiple-Data(SIMD)/vector MAC architecture is presented...
Analog computation traditionally processes information as differences in voltage or current amplitudes. With technology scaling resulting in reduced headroom and limited dynamic range, time-mode computation has emerged as a viable approach for low-power high-precision analog signal processing. Time mode circuits use differences in time to represent information. So far, only linear relationships between...
Lot of applications today employ multipliers to do many simple and complex jobs, from mathematical calculations to signal processing. But we only employ lower order compressors for this operation. This gives us lot of delay. The proposed paper puts to usage, higher order compressors for the same purpose. This results in reduced delay and improves efficiency greatly.
Multipliers are becoming one of the most important basic building blocks in RISC (Reduced Instruction Set Computing), Digital Signal Processor (DSP), graphics accelerators and so on. The speed performance of the multiplier often affects the overall speed performance of a VLSI system. The proposed Dadda tree multiplier (8×8) is used to reduce the computation in the multiplier partial product by the...
This paper presents a low power and high speed 15-4 Compressor for digital signal processing applications. A new 5-3 compressor also proposed which is faster and also consumes less power than the conventional 5-3 compressor. This proposed 5-3 compressor is utilized in 15-4 compressor which will results in low power and high speed. Proposed 15-4 compressor is 11.01% faster and power consumption is...
Subthreshold design has been proposed in the literature as an effective technique for designing signal processing circuits needed in wireless body area network (WBAN) powered by sources with limited energy. The full adder cell forms the basic building block of majority of these signal processing circuits. In this paper, 8-Bit subthreshold Ripple Carry Adders (RCAs) for wireless sensor nodes optimized...
In this paper, we proposed a new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposed CSA tree uses 1's-complement-based...
The residue number system (RNS) is a non-weighted number system which can result in high-speed and low-power implementation of digital signal processing (DSP) computation algorithms. In this paper, an efficient design of the reverse converter for the new three-moduli set {2n-1, 2n, 22n-1-1} is presented. The reverse converter is achieved by an adder-based implementation of mixed-radix conversion (MRC)...
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