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Multiplication is basic function in arithmetic operations. Multiplication based operations such as multiply and Accumulate unit (MAC), convolution, Fast Fourier Transform (FFT), filtering are widely used in signal processing applications. As, multiplication dominates the execution time of DSP systems, there is need to develop high speed multipliers. Ancient Vedic mathematics facilitates the solution...
This paper presents the VLSI Architecture for High-Speed 32-bit Multiplier using Vedic Mathematic sutras. Two sutras among 16 sutras of Vedic Mathematics can be applied for multiplication. Nikhilam Sutra and Urdhva-Tiryagbhyam Sutra are used to implement Vedic Multipliers. In this paper, VLSI architecture for both sutras is implemented and synthesized in Xilinx software. The delay and memory for multiplier...
In the present design algorithms, the speed of the multipliers is limited by the speed of the adders utilised. This work is dedicated for the design of a 16-bit multiplier which is proposed using a vedic sutra named Urdhva Tiryagbhyam from Vedic Mathematics. The 16-bit multiplier is realized using a 8-bit multiplier which inturn realized by a 4-bit multiplier and so on. Modified Ripple Carry Adders[7]...
This paper describes the design of high speed Vedic multiplier that uses the techniques of Vedic mathematics based on 16 sutras (algorithms) to improve the performance. In this paper the efficiency of Urdhva Tiryagbhyam (vertical and crosswise) Vedic method for multiplication which is different from the process of normal multiplication is presented. Urdhva-Tiryagbhyam is the most efficient algorithm...
This paper presents a technique called “Vedic Mathematics” for designing the multiplier that is fast as compared to other multipliers based on mathematical techniques that have been in practice for a long time. A processor's speed depends prominently on its multiplier as multipliers are used in various fields where processing of some signal is essential. Here, a high-speed 8×8 bit multiplier is designed...
Binary multiplication is an important operation in many high power computing applications and floating point multiplier designs. And also multiplication is the most time, area and power consuming operation. This paper proposes an efficient method for unsigned binary multiplication which gives a better implementation in terms of delay and area. A combination of Karatsuba algorithm and Urdhva-Tiryagbhyam...
Floating point multiplication is a crucial operation in high power computing applications such as image processing, signal processing etc. And also multiplication is the most time and power consuming operation. This paper proposes an efficient method for IEEE 754 floating point multiplication which gives a better implementation in terms of delay and power. A combination of Karatsuba algorithm and...
In Digital Signal Processing, the convolution and deconvolution with a very long sequence is ubiquitous in many application areas. The basic blocks in convolution and de-convolution implementation are multiplier and divider. They consume much of time. This paper presents a direct method of computing the discrete linear convolution, circular convolution and deconvolution. The approach is easy to learn...
Decimal data processing applications have grown exponentially in recent years and the IEEE 754-2008 standard for floating point arithmetic has already dictated the importance of decimal arithmetic. In Computer Science where more accurate data processing is demanded, decimal arithmetic plays an important role to support the most accurate data processing at the level of financial and scientific calculations...
Multiplication is an important function in arithmetic operations. A CPU devotes a considerable amount of processing time in performing arithmetic operations. Multiplication requires substantially more hardware resources and processing time than addition and subtraction. Along with the speed its precision also plays a major role. Floating point multipliers provide required precision and they tend to...
Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique computational technique for calculations based on 16 Sutras (Formulae). Novel Binary divider architecture for high speed VLSI application using such ancient methodology is presented in this paper. Propagation delay and dynamic power consumption of a divider circuitry were minimized significantly by removing unnecessary...
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