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The main constraints in recent trends of VLSI technology are power, area and delay. CMOS designs occupy more area and dissipate more power. Power dissipation results in heating up of an IC which directly affects the reliability and performance. Multipliers are the integral part of major application systems like Microprocessor, Digital Signal Processor (DSP) etc., so it is necessary to optimize the...
Floating-point arithmetic plays major role in computer systems. The single precision floating point arithmetic operations are multiplication, division, addition and subtraction. Among all these multiplication is extensively used and involves composite arithmetic functions. The single precision (32-bit) floating point number split into three parts namely Sign part, and Exponent part and Mantissa part...
Vedic mathematics is a system of ancient Indian mathematics, which has a unique technique of solutions based on only 16 sutras or formulae. This technique is very useful for performing tedious mathematical operations at a very fast rate. Motivated by this ancient mathematical system, a high speed low power 8-bit digital multiplier has been proposed in this paper based on Vedic multiplication algorithms...
Vedic maths based multiplier is a novel and high speed multiplier. Adder is one of the main components used in this technique. Using fast adder will enhance the overall performance of the Vedic multiplier. In this work, comparative analysis is done using different adder architectures in Synopsis Design Compiler with different standard cell libraries at 32/28 nm. Various Adder topologies like Ripple...
Present day technology uses many types of multipliers such as Array multiplier, Column and Row Bypassing multiplier. Those multipliers consume more power and occupyan extra area because of its number of blocks. Reducing power dissipation is one of the most critical issues in very large scale integration design today. A sub threshold leakage current plays a dominant role in power dissipation. To rectify...
This paper presents the VLSI Architecture for High-Speed 32-bit Multiplier using Vedic Mathematic sutras. Two sutras among 16 sutras of Vedic Mathematics can be applied for multiplication. Nikhilam Sutra and Urdhva-Tiryagbhyam Sutra are used to implement Vedic Multipliers. In this paper, VLSI architecture for both sutras is implemented and synthesized in Xilinx software. The delay and memory for multiplier...
Multipliers are the important block in digital signal processing, high speed arithmetic logic and accumulate units. Because of the increasing limitations on delay, the importance of faster multiplication is getting increasing. For enhancing the speed of the multiplier design, many new techniques are being worked upon on the multiplier. The Vedic multiplier depends on the Urdhava-Tiryakbhyam sutra...
This paper describes the design of high speed Vedic multiplier that uses the techniques of Vedic mathematics based on 16 sutras (algorithms) to improve the performance. In this paper the efficiency of Urdhva Tiryagbhyam (vertical and crosswise) Vedic method for multiplication which is different from the process of normal multiplication is presented. Urdhva-Tiryagbhyam is the most efficient algorithm...
The proposed multiplier pertaining to concepts of Vedic Mathematics was designed to reduce propagation delay, design complexity as well as to optimize power consumption in comparison to conventional multipliers. A multiplier is a key element in DSP systems, serving as a building block of most computational digital systems, therefore, speed and power consumption are two important parameters of design...
Vedic multiplier is an efficient system for faster result and optimized circuit design. Maintaining higher throughput in arithmetic operations is important to achieve the desired performance in many real-time applications. One of the key arithmetic operations in such applications is to achieve faster multiplication. Vedic Mathematics is one of the fast and low power multiplier. In the present paper,...
In this paper we propose a new architecture for an efficient MAC (Multiplier Accumulator Unit) unit with low area consumption which includes Vedic Square as an alternate component in the MAC unit. Vedic Square is based on the principle of Duplex property of Urdhva Tiryagbhya. Using the proposed architecture, 50% of logic gates are reduced from the basic level of 2*2 bit and 12.64% from 16*16 bit square...
The multiply and Accumulate unit consists of a multiplier unit for multiplication and the product of multiplier is added up with previous result by using an adder. The result of a MAC unit is stored in an Accumulator. MAC is one of the part of digital processing systems. By reducing the delay of multiplier and adder, the overall delay of MAC unit can be reduced. In this paper the MAC unit is designed...
In this paper, area-efficient Vedic multiplier is designed using modified Carry Select Adder (CSLA). As the multiplication is nothing but subsequent addition process, adder is important block in the design of multiplier. Simple Ripple Carry adder (RCA) can be used for implementing multiplier. Digital adder has problem of carry propagation, thus carry select adder is used instead. Carry select adder...
The performance of multiplication in terms of speed and power is crucial for most of the Digital Signal Processing (DSP) applications. Many researchers have come up with various multipliers such as array, Booth, carry save, Wallace tree and modified Booth multipliers. However, for the present day applications Vedic multipliers based on Vedic Mathematics are presently under focus due to their high...
Speed and the overall performance of any digital signal processor are largely determined by the efficiency of the multiplier units present within. The use of Vedic mathematics has resulted in significant improvement in the performance of multiplier architectures used for high speed computing. This paper proposes 4-bit and 8-bit multiplier architectures based on Urdhva Tiryakbhyam sutra. These low...
The Multiply-Accumulator (MAC) unit always lies in the critical path that determines the speed of the overall hardware systems. Therefore, a high-speed MAC that is capable of supporting multiple precisions and parallel operations is highly desirable. This paper describes the implementation of a MAC unit using area efficient Vedic multiplier which enhanced in terms of area and path delay. Speed of...
Multipliers are the key components of systems viz. FIR filters, Microprocessors, Digital Signal Processors etc. which demands high performance. The performance of these applications mainly depends on the numbers of multiplication done in unit time. In real time multipliers the speed and power are the major criteria, thus faster and power efficient multipliers are needed. This paper focuses on the...
This work synthesises high performance integer multiplier designs suitable for high speed reconfigurable VLS I systems. Various designs of integer multipliers are taken and are compared on the basis of area and speed and the design most suited for the given FPGA platform is understood. The designs are implemented on Virtex FPGA and the comparisons in terms of area and speed are made. The multiplier...
In this paper, a high speed and low power 16×16 Vedic Multiplier is designed by using low power and high speed modified carry select adder. Modified Carry Select Adder employs a newly incremented circuit in the intermediate stages of the Carry Select Adder (CSA) which is known to be the fastest adder among the conventional adder structures. A Novel technique for digit multiplication namely Vedic multiplication...
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